Mig7 project Debugging with ILA core - Timing Error in implementation

Question

Hello,
I am designing a core which has only performing read/write operations to/from DDR3 SDRAM with MIG7 IP core. I am synthesizing and implementing without any problem if I have no ILA core present in the project. After adding the ILA core I am having errors at implementation (Route Design). I used Set up Debug wizard while creating cores and .xdc file.
After several trials I have seen 2 types of errors:
[Drc 23-20] Rule violation (PDRC-29) MMCM_adv_ClkFrequency_clkin1 - The calculated frequency value, 0.000 MHz, of the CLKIN1_PERIOD attribute on the MMCME2_ADV site MMCME2_ADV_X1Y1 (cell tranceiver/u_mig_7series_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) is outside the allowed range (10.000 - 933.000 MHz). Please change the CLKIN1_PERIOD attribute value in order to be within the allowed range for this device.
[Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 500.000 MHz (CLKIN1_PERIOD, net CLK) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y0 (cell dbg_hub/inst/USE_DIVIDER.U_GT_MMCM) falls outside the operating range of the MMCM VCO frequency for this device (600 - 1440 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (10.000000), multiplication factor CLKFBOUT_MULT_F (5.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.
[Vivado_Tcl 4-16] Error(s) found during DRC. Router not run.
In xdc file I have changed two parameters:
set_property C_CLK_INPUT_FREQ_HZ 200000000 [get_debug_cores dbg_hub] -- it was 300000000 before as default
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub] -- it was false
I added xdc file and error description in the attachments.
I could not find any solution.
Best regards, Ali

Answer 1

I guess I have solved the problem, if it is a problem.
In the description of the property, C_CLK_INPUT_FREQ_HZ,  it says that "this property is only used when C_ENABLE_CLK_DIVIDER property is set true". However when I set true it gives clock frequency error as I have given in the error description.
Then I have set C_ENABLE_CLK_DIVIDER property to false and then tried with that. And everything gone well. The project is working as I intented.
I guess there is a mistake in the explanation or I just misunderstood the sentence.
Thanks for the previous replays.