Cannot read data in FPGA
Hi guys, I have a code that I developed for reading in digital data through digital lines in a PXI-7813R. But unfortnately, in the Host vi, I cannot acquire any data, even though I have fed in an external signal to the digital line in the PXI through a connector.
I have a data graph to display this signal, but nothing can be seen when I run the problem! Anyone know what the problem is?
I have attached the project.
ANy help would be great.
Thanks, Anoop
Solved!
Go to Solution.
Attachments:
Digital Input FPGA.lvproj 100 KB
FPGA.vi 79 KB
Host.vi 81 KB
Hi, thanks for the reply.
I have a couple of questions though. I dont understand what you mean in the first line. I have set the READ in the FPGA VI to be true so that when it is pressed, data can be read from the HOST VI.
Now, getting on to the issues you highlighted.
1. I have included a polling delay and the error issue is now sloved. But, when you mean "Also make sure you wire your error in to the while loop stop condition....", I have did this using the polling. Is this OK?
2. You mention "In your vi, you are writing...." do you mean in the FPGA? If so, I have set the "read?" flag on the case structure, to use it as a switch for teh true conditon. is this not correct?
I have attached the modified Project along with this. Feel free to edit it if you feel the urge too
Attachments:
Digital Input FPGA.lvproj 91 KB
Host.vi 99 KB
FPGA.vi 199 KB
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