DMA FIFO number of elements to read mismatch in FPGA and RT

Hi all
I am using myRIO , LV14 to run my application.
Application: I have to continuously acquire data via FPGA and process in RT host once every 2000 samples are collected. I use DMA FIFO (size 8191) to acquire data, use timeout property at the FPGA to eliminate buffer overflow. I had followed cRIOdevguide to implement this part. A snippet of what I have implemented is attached. Whole code runs in SCTL at 50MHz.
Issue: Twice or thrice I encountered with this strange behaviour, that the FPGA FIFO is giving continous timeout and the RT is unable to read the FIFO. The number of elements to write propery in FPGA VI gives 0 showing that FIFO is full and no more can be written, but at the RT, elements remaining is giving 0, hence it is reading 0 (no) elements.
Workaround: I put a case where I will write to FIFO (as per the code) and if the number of elements to write is nonzero. It seems to work fine, as of now.
What confuses me is that my FPGA VI says that FIFO is full (FIFO number of elements to write = 0) and gives a timeout error, but RT VI says that number of elements remaining in FIFO is 0 and hence no data is read. Any idea why it is so? My FPGA and RT VIs continues to run, but with no data being acquired or read.
I saw this behaviour within minutes after running the code. Any idea as to why it is happening? I am trying to reproduce the behaviour and will update if i again encounter with it. Sorry, I cannot post my code here, but i guess the code snippets explain it to some extend.
Thanks
Arya
Edit: Even with the mentioned workaround, the problem persists, now that the FPGA does not write to FIFO at all. And the RT VI is not able to read any elements as it sees 0 elements in the FIFO. The FIFO continues to be in timeout state. So i guess the problem is with the RT side.
Solved!
Go to Solution.
Attachments:
cRIOdevguide_FIFOreadwrite.PNG ‏107 KB
FPGA_FIFO_write.PNG ‏41 KB
RT_FIFO_read.PNG ‏39 KB

Hi Nathan
Yes, I could have replaced it with an OR. Regarding my application, I want to acquire data in chunks of 2000 samples. If at all I receive a timeout error, I want to discard that chunk of 2k samples and start all over again. So my logic was like this, I acquire the data, if there is a timeout, the reset is triggered, and the system waits to comeback from reset, and it starts acquiring again. Btw, I tried removing the multiple FIFO reads in RT, but the error is still the same.
I have a small doubt as well, if I do not want to obtain stale data at alI, I would just check if timeout occurs, empty my FIFO and start acquiring data again (no reset button), isnt it? This was my original logic, but I saw that after a while, it stopped acquiring data and timeout led was on. I was thinking that FPGA and RT was simultaneously trying to acquire FIFO which might cause timeout. Somehow, I now feel that, as you have pointed out, my code is overly complicated. I will modify it and update the results. Thank you!
Arya

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ok so I got my answer, its actually the default depth of the DMA FIFO.
Maximum size of this FIFO is set to be 1023, which is coerced to a value of 1029. I did a mistake in the picture (posted in last msg), Here is the correct one;
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KUDOS ARE WELCOMED.
If your problem get solved then mark as solution.
Attachments:
FPGA VI.jpg ‏205 KB
FPGA 2.png ‏92 KB
Host VI.jpg ‏168 KB

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Solved!
Go to Solution.

What type of data do you want to transfer over the FIFO? As in how many bits does each sample contain.
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Go to Solution.

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