Cascade 2 PLL_ADV in spartan-6 FPGA and dynamic reconfigure

Can I cascade 2 PLL_ADV in spartan-6(XC6SLX25T) FPGA  and dynamic reconfigure them?

Hi, , Of course the two PLL_ADV meet the requirements for VCO frequency. The output of first PLL_ADV connect to a BUFG and then to the CLKIN of the second PLL_ADV.
You mean that if change the first PLL_ADV output with dynamic reconfigure, I must reset the second PLL_ADV and then dynamic reconfigure it ?

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  • Cascade 2 PLL_ADV in spartan-6 FPGA and dynamic configure

    Can I cascade 2 PLL_ADV in spartan-6(XC6SLX25T) FPGA  and dynamic configure them?

    Hi, , Of course the two PLL_ADV meet the requirements for VCO frequency. The output of first PLL_ADV connect to a BUFG and then to the CLKIN of the second PLL_ADV.
    You mean that if change the first PLL_ADV output with dynamic reconfigure, I must reset the second PLL_ADV and then dynamic reconfigure it ?

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    I'd like to make a correction to the article. It's the University of Zürich who has developed the plug-in cRIO White Rabbit module. The EN-ICE-MTA section at CERN has tested the performance of the module and organised the meeting.

  • Erasing Flash Memory of Spartan 3E FPGA

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  • Is the Nexys2 board (with spartan 3e FPGA) compatible with the FPGA module

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  • Spartan 3e Fpga

    Hi  Guys,
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  • Project spartan does work and give amassege

    project spartan does work and give amassege  no internet but the other brawsets work 

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  • DMA FIFO number of elements to read mismatch in FPGA and RT

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    Attachments:
    cRIOdevguide_FIFOreadwrite.PNG ‏107 KB
    FPGA_FIFO_write.PNG ‏41 KB
    RT_FIFO_read.PNG ‏39 KB

    Hi Nathan
    Yes, I could have replaced it with an OR. Regarding my application, I want to acquire data in chunks of 2000 samples. If at all I receive a timeout error, I want to discard that chunk of 2k samples and start all over again. So my logic was like this, I acquire the data, if there is a timeout, the reset is triggered, and the system waits to comeback from reset, and it starts acquiring again. Btw, I tried removing the multiple FIFO reads in RT, but the error is still the same.
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  • LV2012 crashes when opening LV2010 project containing OOP and dynamic FPGA references

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    LV2012_Crash.PNG ‏22 KB

    Thank you for your response, but the Discussion Forums link that you provided refers to a problem that occurs when exiting a running executable. My problem is different. I am simply opening up a LV2010 project using LV2012. No running of my program is involved.
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  • Servo motor control using CRIO+FPGA and 9477 digital out module

    Hello experts,
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  • How to create a virtual FPGA and run LabVIEW code on it?

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    If I've understood correctly, you have LabVIEW code written for an FPGA and running on an NI FPGA board, which you'd now like to run in a simulated system.  I doubt this is possible since I don't think there is a way for you to simulate all the hardware (DAQ and whatever else) that is attached to the FPGA on the real hardware.  Also, LabVIEW doesn't have any way of accessing an arbitrary non-NI FPGA target and without the LabVIEW interface I don't think your FPGA code will be too useful.

  • FPGA and DAQ card synchroniz​ation

    Hi, we are controlling and acquiring data from multiple hardware devices (including translational stages and photodetectors). Until last week, we used to peform all control and acquisition using a PCIe 7852R FPGA board. However, we decided to switch the acquisition part to a PCIe 6363 DAQ card to improve the voltage resolution. During testing, I found that the internal clocks in the FPGA and the DAQ cards are slightly mismatched (not just a phase delay, but a difference in time-period).
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    Hi GerdW,
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    Varun

  • Using FPGA and Labview without RIO board.

    Dear Sir
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    Thanks a Regards

    Hooovahh wrote:
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