FPGA and DAQ card synchroniz​ation

Question

Hi, we are controlling and acquiring data from multiple hardware devices (including translational stages and photodetectors). Until last week, we used to peform all control and acquisition using a PCIe 7852R FPGA board. However, we decided to switch the acquisition part to a PCIe 6363 DAQ card to improve the voltage resolution. During testing, I found that the internal clocks in the FPGA and the DAQ cards are slightly mismatched (not just a phase delay, but a difference in time-period).
I know this because I generated a square wave (period = 20us) using the FPGA and acquired it using the DAQ card (at a rate of 200kHz, i.e., 1 sample every 5us). I observed that the acquired square shifts by 5us every 5 seconds or so. Such a shift does not occur if the generation and acquisition is done using the same board. Therefore, the only explanation is that the clock frequencies of FPGA and DAQ cards differ. According to my calculation, percentage difference between their clock times must be 5us/5s = 0.0001%. 
Therefore, I am wondering if there is anyway to synchronise the clocks between them. Or, is there a way I can drive the DAQ device based on the FPGA clock, or vice versa? Also, please let me know if there is something trivial that I have fix.
Thank you very much.
Regards,
Varun
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Answer 1

Hi GerdW,
Thank you for your reply. 
I understand both solutions you have suggested. I had conceptually thought about the first one (to control the sampling rate). However, I still haven't figured out how to accurately generate a 200kHz square wave - I think I can figure that one out this morning.
However, I am unsure how to implement the second option. I presume the default internal clock inside the DAQ is running at 100MHz or so. Therefore, inorder to obtain the same performance while using an external clock, I would have to generate at least a 80MHz TTL clock-out from the FPGA. Could you please tell me how I can do that? I couldn't find any clock-out capabilities on my FPGA. Or would I have to generate a clock of my own using Single-Cycle-Timed-Loops?
Not only did you provide two different solutions, your reply suggested that I wasn't wrong in interpreting that the clock periods of our FPGA and DAQ must be slightly off. 
Thank you very much.
Regards,
Varun