Choose DDR3 interface between PL

Hi,
I'm using an evaluation board with the ZC702 SoC. I want to process video stream with pclk = 40 MHz and my system now is working at 160 MHz.
For processing video I need to do an interpolation for each pixel (1280*720). The problem is that the weights of these interpolations are stored in the DDR3 exactly I need 2 coefficients of 32 bits foreach pixel. Actually I have a VDMA that reads one image stored in DDR3 and show it in a video panel this part works well.
My problem is when I try to read the 2 coefficients for doing the interpolation. I have tried doing it by using a simple AXI Master interface but I have problems with the synchronization (the coefficients arrives to the interpolation part too late). Now I'm going to try with a more sophisticated Xilinx's IP core, but i don't know what is the best option to achieve my purpose.
I'm thinking in two candidates first of all DataMover but I dont know how to send the commands (I have to create a module that send the commands or Xilin's provides an IP core to send it) and what is the maximum amount of data that can be transferred by DataMover (In my case I need to move 7372800 bytes of data). The other candidate is use a VDMA (but I think it is a waste of resources)
Thank you for your replies

Hi,
Yes i asserted the tvalid first and then wait for the tready.
I have found a reason for this strange behaviour. It seems that the datamover is on reset state and in the product guide appears a m_axi_mm2s_aresetn signal but when I import the IP core (only mm2s) this signal doesn't appear.
This is because in the .mpd file of the datamover appears an error related with the m_axi_mm2s_aresetn signal. I have upload a picture where you can find the problem. It means that the m_axi_mm2s_aresetn signal only appears if the s2mm side is enabled.
I don't know if it is an issue or this is for some reason that I don't understand. Where do I have to report this circumstance?
Thank you,

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Moderator message: "spec dumping", please work yourself first on your requirement.
locked by: Thomas Zloch on Sep 24, 2010 1:41 PM

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Choose DDR3 interface between PL

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