Compilation time - LabVIEW FPGA project

I am trying to compile a LabVIEW FPGA project over NI PXIe-1071 chassis.
My problem briefly lies in the compilation time which last hours while only takes approximately 20 minutes on another chassis I am having with exactly the same specifications.
Is there any project settings I should check which may casuing this problem ?
Thanks.

The FPGA boards exactly the same and the VI is exactly the same? All you are changing is the chassis? R Series or FlexRIO? What version of LabVIEW FPGA? How much are the designs "filled up" (like what is the percent utilization of slices)? There are project settings for effort levels of the Xilinx tools depending on what version of LabVIEW you are using.

Similar Messages

Incremental Compile LabVIEW FPGA

Hello all.
It is time-consuming that we have to compile all LabVIEW FPGA code even if there is tiny little change on FPGA code.
I understand there is sampling probe, Desktop execution node and simulation tools to reduce such time.
Our customer in Japan, would like to use incremental compile function also on LabVIEW.(Please see below)
I agree his opinion.
http://www.youtube.com/watch?v=9v50uCVdW3o
What do you think?
Eisuke Ono
Application Engineer at National Instruments Japan.

I think this is something everyone would like to see, I'm glad someone finally posted an idea for it to get feedback from the community. With the introduction of (better) incremental compilation in the latest 3rd party tools like Xilinx there is certainly some features the LabVIEW FPGA compiler could take advantage of. There is also plenty of optimizations within the LabVIEW FPGA compiler itself that could help.
The problem with incremental compilation of any kind is doing it well enough that the majority of use cases don't suffer performance issues when squeezing application changes into as few changes in the actual hardware. Getting this balance right takes a lot of work and a lot of sample applications to try it against.

Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
·         The Code size and speed optimization.
·         Developing time.
·         Compiling time.
·         Verifying time.
·         Ability to developing in future.
·         …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
Go to Solution.

Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

LabView fpga VHDL code and compiler

Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.

Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer

"LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD

The compilation of my labview fpga vi fails with the error message "LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD".
In the 'final timing (place and route)' report, the requested frequencies are all below the maximum frequencies and the compilation error message is only displayed at the very end on the 'summary' page.
I tried to optimize my labview fpga vi with pipelining, but had no success.
Can anybody offer some advice on how to debug fpga code with this error? Is this really a timing error or something else?
Software:
Labview 2011, fpga 2011, xilinx tools 12.4 sp1
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
The Xilinx log of the compilation run is attached.
Also, this issue was already discussed in this thread ~6 months ago, but no satisfying answer was offered so far...
Thanks,
Fabrizio
Attachments:
xilinxlogc.txt ‏2313 KB

Hi Kyle,
the problem is: I have one computer which compiles the VI successfully and a second one which shows that error. Both use the same software setup (LV2011SP1+RT+FPGA from DS2012-01). Both use the same project file - atleast SVN shows no difference.
- You can have one FPGA VI where one computer is compiling successful and a second one complains. (Btw. I have a SRQ running in Germany on this topic.)
- More problems: After successful compiling on first computer and transferring all to second computer (using SVN, including the full project folder with all files like bitfiles, lvproj, and everything) the second computer is unable to start the RT executable due to error "FPGA VI needs to recompile". Solution so far: Call the FPGA-OpenReference with the bitfile instead of the VI (as I used to do until now)...
- More problems: After modifying the FPGA-OpenReference to use the bitfile (on the 2nd computer) and transferring all the files back to the 1st computer (using SVN as before, including the whole project) the 1st computer complains: FPGA-OpenReference is creating a different reference than is used in the VI. So what happens here? On one computer my VI is ok, the reference is typed correctly. Transferring all the files to a different computer the VI isn't ok anymore due to changes of the reference??? You know: all files are the same: lvproj, FPGA bitfile didn't change, cRIO reference didn't change...
All those problems didn't occur on my RT-FPGA projects in LV2010SP1. I'm not pleased...
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

Labview FPGA compile stuck at "Place and Routing"

I am using LabVIEW 2010 SP1 32-bit FPGA module. I've built a very large program that was first done back using LabVIEW 8.6, so I have several years experience on LabVIEW FPGA.
When I say it's a large program, I mean that a several times over the last couple years I've tried to add more functionality that has failed to compile do to not enough space on the target or timing restraints. My target has mostly been the PCI/PXI NI-7813R. Due to the nature of our product, a lot has to be done on one FPGA board.
When I do go "over the limit" the compile (after a couple hours) fails and tells me that there's just not enough room on the 7813.
Recently, however, I added some more code, thinking the odds were good that it might push me over the edge. However, the compile never fails. Unfortunately, it never stops either. It gets to the "Placing and routing" portion of the compile and just stays there. When I say stays there, I mean I've run it over night, and when I check it the next morning, the "Elapsed time" is over 10 hours, and still counting up. The device utilization and estimated timing numbers are all under max. And I see no errors in the report so far that I'm used to seeing. Like I said, it just keeps compiling.
I've attached the Xilinx log. It looks much like the log before I added the extra code, except it just stops logging with reporting any useful error.
Anyone have an idea what I could be doing wrong?
Thanks,
Rick
Attachments:
XilinxLog.txt ‏3936 KB

tannerite,
Thanks for your response.
I added code that measures the "on time" of incoming DIO pulses. If the pulses are HIGH for one given amount of time (eg. 60[+/- 5] usecs) it means one thing, if HIGH for a different amount of time (eg. 120[+/- 5] usecs) it means something else. Generally speaking, I just keep a tick count between the rising and falling edge of the pulse, and use the "In Range and Coerce" from the Comparison Functions palette to check where the count lies.
When it compiled successfully, I duplicated the above code for 10 seperate DIOs. Then I realized I needed to monitor 20 DIOs. It was when I added the code for these extra 10 DIOs that I got the "forever" compile. The compile problem occurs everytime I try to compile with the extra 10 DIO code in place. As an experiment, I just added 4 extra DIOs, i.e. code to monitor a total of 14 DIOs. This causes the same compile problem.
And yes, the compile seems to hang in the same place every time it hangs. Like I said, I wouldn't be surprised if I'm just beyond the available resources available. But when I've done this in the past, the compile does finally fail, and I get a useful error message. I've never seen it go "forever".
Thanks ahead of time for any insight you might have.
- Rick

How can I reduce FPGA compiler time

Hi,
I am trying to implement a PID control loop on the FPGA of a cRIO.
The VI which runs on the FPGA target takes very long to compile (1h+).
Does anyone have an idea while the compilation takes so long and how I might be able to inprove compilation time?
The program can be found in attachment.
Best regards,
Jasper
Attachments:
PID FPGA TEST.zip ‏160 KB

Hi Jasper,
FPGA's normally take a very long time to compile compared to software compilations. 1 hour sounds about right for a slightly above average sized project. Compile times of anywhere from 2-4 hours (and longer for larger devices!) are not unheard of.
Companies who are serious about FPGA compilation and rely on quick turnaround invest in servers which contain many computers to work on the compilation (this is also why when you compile, it asks you if you would like to compile on the "local sever" (your computer) or an external server).
NI also has a cloud compiler available that will let you compile your code on their servers, however you must pay for the time. I think they offer a free trial if you wanted to see how it works.
So if you seriously need quick turnaround, you must consider some serious hardware.
Otherwise, you will have to queue up multiple compilations and let them run overnight like the rest of us.
www.movimed.com - Custom Imaging Solutions

Long FPGA compilation time ( 30 hrs)

I am writing some small test programs to check a PXI-7831R FPGA card.
One program is a FOR loop inside a WHILE loop with a single AI read. I run the FOR 1000 times, then output a 1000-element array of 16-bit AI values through auto-indexing. This program compiled for 31 hours and 15 minutes before I aborted.
Is there a reason for such a long compile time (too large an array)?
Are there certain programming architectures that I should avoid on FPGA (e.g., nested loops)?
I am running LVRT7.1 on a PXI-8145RT. There is also a 7350 motion board installed, though not used in this program.
Thanks.
Laine

I've read somewhere in the FPGA documentation that arrays in FPGA applications should be limited to 32 elements. The consume a large amount of space on the chip, so you need to be careful when using them.
Ed
Ed Dickens - Certified LabVIEW Architect - DISTek Integration, Inc. - NI Certified Alliance Partner
Using the Abort button to stop your VI is like using a tree to stop your car. It works, but there may be consequences.

Is there a 'compile time' if/else statement in LabVIEW

I have some LabVIEW software that includes subVIs to read from and write to digital IO lines. However, I need to also be able to run this software on systems which don't have an IO card (or associated drivers) installed and so I want to be able to allow the software to be on PCs that do or don't have the drivers installed.
Optimally, I would like to modify the software so that at runtime, by reading the settings in a configuration file, a boolean is set to determine whether the IO functions are called. I tried this but, unfortunately, am getting error messages when I try and start up the software due to the lack of the 'nidaq32.dll' file on the target PC. I'm guessing this is because the subVIs are only within case structures and so must be loaded into memory regardless of whether they are to be used.
Is there any way around this problem? If I were writing this in C I guess I would use '#if' statements to include/exclude the IO functions at compile time. Is there an equivalent in LabVIEW? I guess my options are:
1. Finding some way of allowing the IO functions to be included at runtime though I'm thinking this might not be possible.
2. Include/exclude the IO functions at compile time with some LabVIEW equivalent of the C '#if' preprocessor directive.
3. Give in and install the nidaq32.dll file with the software.
Just to complicate matters, I'm currently running LabVIEW 5.0.1 (I do plan to upgrade soon) so am limited to the functions available in this version.
Thanks.

CAS wrote:
Just to complicate matters, I'm currently running LabVIEW 5.0.1 (I do plan to upgrade soon) so am limited to the functions available in this version.
That's the main problem.
On newer versions you can:
define simulated devices (http://zone.ni.com/devzone/cda/tut/p/id/3698)
use the conditional disable structure (see e.g.: http://zone.ni.com/devzone/cda/tut/p/id/3046, (see section 6))
Time to upgrade!
Message Edited by altenbach on 06-21-2007 07:32 AM
LabVIEW Champion . Do more with less code and in less time .

Trying to dynamically load CSS for project at compile time via config XML file to select CSS file.

I'm using the same code base to compile different versions of a project. Each project has different base fonts. I've created multiple css files that use the same style names. The idea being that in the code I reference the style names, then the loaded CSS determines which font (and size, color, etc) is used for each style name.
The CSS files are compiling to SWFs, and those SWFs are referenced in config.xml files. Before compiling, I select the config file to use.
I am loading the CSS SWF files via the StyleManager in the Application.mxml, like so:
styleManager.loadStyleDeclarations( _contentData.elements( 'cssPath' ).@path )
The path traces out correctly as:
assets_embed/styles/project2.swf
For some reasone I must include an fx:Style line in the Application.mxml file or no fonts are recognized. Example:
<fx:Style source="assets_embed/styles/project1.css"/>
If I reference the css for project one (as done above) then most, but not all, styles work. Some styles reference the fonts from the project 1 css, others properly use fonts from project 2 swf. If I point to the CSS for the project I'm compiling in the <fx:Style > tag then all fonts work, but that defeats the goal of using XML rather than code to identify the styles.
So, why do I need the fx:Style line if the css is being loaded via StyleManager?
Why is there "cross talk" between style definitions?
Is there a better way to select styles at compile time?

I read this quickly so I might have missed a detail. I think your describing an issue with recent Flex releases that is described in the fine print somewhere. If you don't have any fonts embedded in the main app and are only bringing in fonts embedded in CSS SWFs, you have to force-link the EmbeddedFontRegistry by adding something like this to the main app's script block.
import mx.core.EmbeddedFontRegistry; EmbeddedFontRegistry;
(Yes, "EmbeddedFontRegistry" is in there twice, once to define the fully qualified name, the other to create a class dependency to force the linking).

Xilinx version availability for labview fpga compile

While trying to compile a Labview vi for target NI PXI 7831R, at first I didn't have
any Xilinx compile so I asked my network guy to instal it. Now it complains
that it needs 10.1 when 11.5 is available. I asked him to install the 10.1 and
he did but it isn't available to the NI FPGA compile worker. How do I solve
this?
thanks

Hi DonQuixote,
You are correct in that the PXI 7831R requires Xilinx Compile Tools 10.1. This is because this card has a Vertex II chip. You can read more about Xilinx requirements here: http://ae.natinst.com/public.nsf/webPreview/A4B20D58C051DFB386257A56007BB0B2?OpenDocument .
Have you uninstalled version 11.5? What version of LabVIEW do you have? Are you recieving an error or some other message? If so, please post a screenshot.
Thanks!
Dayna P.

LabVIEW FPGA: The compilation failed due to a xilinx error

I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd ignored due to errors
-->
Total memory usage is 204688 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
Compilation Time
Date submitted: 2014/2/26 18:15
Date results were retrieved: 2014/2/26 18:17
Time waiting in queue: 00:06
Time compiling: 02:02
- PlanAhead: 01:16
- Core Generator: 00:00
- Synthesis - Xst: 00:35
Solved!
Go to Solution.

I have got the same error, Have you solved this error?
What you have done?
jasonneu wrote:
I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd ignored due to errors
-->
Total memory usage is 204688 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
Compilation Time
Date submitted: 2014/2/26 18:15
Date results were retrieved: 2014/2/26 18:17
Time waiting in queue: 00:06
Time compiling: 02:02
- PlanAhead: 01:16
- Core Generator: 00:00
- Synthesis - Xst: 00:35
Mahran

Can anyone provide me the suitable material for labview fpga &labview real time??

Message Edited by Sithu on 05-27-2008 04:32 AM

The following link includes training material for both LabVIEW Real-time and LabVIEW FPGA.
http://zone.ni.com/devzone/cda/tut/p/id/6929
If you are new to LabVIEW you should start from the LabVIEW Basics material available at the following link.
http://cnx.org/content/col10241/latest/
KostasB
NIUK Applications Engineering

LabVIEW FPGA was unable to contact the Compile Server at "localhost" on port 96.

Hi,
The following error occured when i am trying to compile my design on labview fpga 8.6, and the error reads as follows.
"LabVIEW FPGA was unable to contact the Compile Server at "localhost" on port 96. The server name or port may be incorrect, a firewall may be blocking communications with the server, or the configured timeout may be too low. You may reconfigure Compile Settings by clicking the Configure button or try contacting the Compile Server again by clicking the Retry button. Click the Cancel button to abort."
Can ane one help me in sorting out this error.,
Regards
KalyanSuman KV

This should solve it

Qual a diferença do LabVIEW FPGA e o LabVIEW REAL- TIME?

Hello,
Could anyone help me? This question arose in my work and could not answer. Does anyone know tell me?
Thank you.
Solved!
Go to Solution.

Olá,
Com o LabVIEW FPGA você programa diretamente o chip FPGA presente no chassis cRIO, placas da NI Série R e single Board RIO. Você programa as E/S diretamente no chip, sendo assim uma programação de mais baixo nível. A grande vantagem do FPGA é o "paralelismo real", o que garante altas velocidades na execução das rotinas programadas.
Assista ao webcast Introduction to LabVIEW FPGA
Com o LabVIEW Real-Time você desenvolve aplicações que são críticas em relação a "tempo". Chamamos de aplicações "deterministicas". A idéia é que, se você tem uma rotina que deve ser executada em um tempo determinado, a diferença entre o tempo real e o que você programou seja o menor possível. Aplicações em Computadores comuns não são deterministicas, pois enquanto o LabVIEW executa uma certa rotina programada, o Windows está executando outras tarefas, monitorando a utilização de periféricos, atualizando a tela, etc.
Real time não significa "Velocidade", mas "Confiabilidade".
Assista ao webcast LabVIEW Real-Time: Graphical Development, Hard Real-Time Performance
Hello,
With LabVIEW FPGA you program the FPGA chip itself. The FPGA chip is found into cRIO chassis, NI R-Series Boards, and NI Single board RIO. You program the I/O directly in the chip, so we consider this as a low level programing. The main FPGA advantage is the "Real Paralelism", which guarantees high speed execution programming.
Whatch Introduction to LabVIEW FPGA webcast
With LabVIEW Real-Time you develop called "time crictical" or "Deterministics" applications. In case of you routine must be executed in a specified period of time, the difference between the real time execution and the time you programmed is as low as possible. Commom computers programming are not deterministic, because in the meantime of executing a certain programmed routine, the OS (e.g. Windows) is running other appication tasks, monitoring peripherals like mouse and keyboard, uptading screen, etc.
Real-Time doesn't mean "faster" but "reliable".
Watch LabVIEW Real-Time: Graphical Development, Hard Real-Time Performance webcast
I hope the information helps you!
Best Regards
Felipe Flores
Engenharia de Aplicações
National Instruments Brasil

Compilation time - LabVIEW FPGA project

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