Incremental Compile LabVIEW FPGA

Hello all.
It is time-consuming that we have to compile all LabVIEW FPGA code even if there is tiny little change on FPGA code.
I understand there is sampling probe, Desktop execution node and simulation tools to reduce such time.
Our customer in Japan, would like to use incremental compile function also on LabVIEW.(Please see below)
I agree his opinion.
http://www.youtube.com/watch?v=9v50uCVdW3o
What do you think?
Eisuke Ono
Application Engineer at National Instruments Japan.

I think this is something everyone would like to see, I'm glad someone finally posted an idea for it to get feedback from the community. With the introduction of (better) incremental compilation in the latest 3rd party tools like Xilinx there is certainly some features the LabVIEW FPGA compiler could take advantage of. There is also plenty of optimizations within the LabVIEW FPGA compiler itself that could help.
The problem with incremental compilation of any kind is doing it well enough that the majority of use cases don't suffer performance issues when squeezing application changes into as few changes in the actual hardware. Getting this balance right takes a lot of work and a lot of sample applications to try it against.

Similar Messages

Error in compiling LabVIEW FPGA target

Hi I get the attached error when I build my LabVIEW project.
I use Xlinx 14.7 to complie the code and the code is developed in LAbVIEW 2013 fp2
I also use NI DlexRIO 14, NI-RIO 14.0.1
Thanks
Attachments:
123.jpg ‏99 KB

I changed the server to local from Tools\Options\FPGA Module
But still when I compile it I get this error message. I still can't compile it because it asks for Xilinx 14.4
I have also downloaded 14.4 but I can't insall it because as soon as I try to insatll I get teh attached error
Attachments:
Untitled.jpg ‏125 KB
Untitledwq.jpg ‏45 KB

"LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD

The compilation of my labview fpga vi fails with the error message "LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD".
In the 'final timing (place and route)' report, the requested frequencies are all below the maximum frequencies and the compilation error message is only displayed at the very end on the 'summary' page.
I tried to optimize my labview fpga vi with pipelining, but had no success.
Can anybody offer some advice on how to debug fpga code with this error? Is this really a timing error or something else?
Software:
Labview 2011, fpga 2011, xilinx tools 12.4 sp1
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
The Xilinx log of the compilation run is attached.
Also, this issue was already discussed in this thread ~6 months ago, but no satisfying answer was offered so far...
Thanks,
Fabrizio
Attachments:
xilinxlogc.txt ‏2313 KB

Hi Kyle,
the problem is: I have one computer which compiles the VI successfully and a second one which shows that error. Both use the same software setup (LV2011SP1+RT+FPGA from DS2012-01). Both use the same project file - atleast SVN shows no difference.
- You can have one FPGA VI where one computer is compiling successful and a second one complains. (Btw. I have a SRQ running in Germany on this topic.)
- More problems: After successful compiling on first computer and transferring all to second computer (using SVN, including the full project folder with all files like bitfiles, lvproj, and everything) the second computer is unable to start the RT executable due to error "FPGA VI needs to recompile". Solution so far: Call the FPGA-OpenReference with the bitfile instead of the VI (as I used to do until now)...
- More problems: After modifying the FPGA-OpenReference to use the bitfile (on the 2nd computer) and transferring all the files back to the 1st computer (using SVN as before, including the whole project) the 1st computer complains: FPGA-OpenReference is creating a different reference than is used in the VI. So what happens here? On one computer my VI is ok, the reference is typed correctly. Transferring all the files to a different computer the VI isn't ok anymore due to changes of the reference??? You know: all files are the same: lvproj, FPGA bitfile didn't change, cRIO reference didn't change...
All those problems didn't occur on my RT-FPGA projects in LV2010SP1. I'm not pleased...
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

Labview FPGA compile stuck at "Place and Routing"

I am using LabVIEW 2010 SP1 32-bit FPGA module. I've built a very large program that was first done back using LabVIEW 8.6, so I have several years experience on LabVIEW FPGA.
When I say it's a large program, I mean that a several times over the last couple years I've tried to add more functionality that has failed to compile do to not enough space on the target or timing restraints. My target has mostly been the PCI/PXI NI-7813R. Due to the nature of our product, a lot has to be done on one FPGA board.
When I do go "over the limit" the compile (after a couple hours) fails and tells me that there's just not enough room on the 7813.
Recently, however, I added some more code, thinking the odds were good that it might push me over the edge. However, the compile never fails. Unfortunately, it never stops either. It gets to the "Placing and routing" portion of the compile and just stays there. When I say stays there, I mean I've run it over night, and when I check it the next morning, the "Elapsed time" is over 10 hours, and still counting up. The device utilization and estimated timing numbers are all under max. And I see no errors in the report so far that I'm used to seeing. Like I said, it just keeps compiling.
I've attached the Xilinx log. It looks much like the log before I added the extra code, except it just stops logging with reporting any useful error.
Anyone have an idea what I could be doing wrong?
Thanks,
Rick
Attachments:
XilinxLog.txt ‏3936 KB

tannerite,
Thanks for your response.
I added code that measures the "on time" of incoming DIO pulses. If the pulses are HIGH for one given amount of time (eg. 60[+/- 5] usecs) it means one thing, if HIGH for a different amount of time (eg. 120[+/- 5] usecs) it means something else. Generally speaking, I just keep a tick count between the rising and falling edge of the pulse, and use the "In Range and Coerce" from the Comparison Functions palette to check where the count lies.
When it compiled successfully, I duplicated the above code for 10 seperate DIOs. Then I realized I needed to monitor 20 DIOs. It was when I added the code for these extra 10 DIOs that I got the "forever" compile. The compile problem occurs everytime I try to compile with the extra 10 DIO code in place. As an experiment, I just added 4 extra DIOs, i.e. code to monitor a total of 14 DIOs. This causes the same compile problem.
And yes, the compile seems to hang in the same place every time it hangs. Like I said, I wouldn't be surprised if I'm just beyond the available resources available. But when I've done this in the past, the compile does finally fail, and I get a useful error message. I've never seen it go "forever".
Thanks ahead of time for any insight you might have.
- Rick

Compilation time - LabVIEW FPGA project

I am trying to compile a LabVIEW FPGA project over NI PXIe-1071 chassis.
My problem briefly lies in the compilation time which last hours while only takes approximately 20 minutes on another chassis I am having with exactly the same specifications.
Is there any project settings I should check which may casuing this problem ?
Thanks.

The FPGA boards exactly the same and the VI is exactly the same? All you are changing is the chassis? R Series or FlexRIO? What version of LabVIEW FPGA? How much are the designs "filled up" (like what is the percent utilization of slices)? There are project settings for effort levels of the Xilinx tools depending on what version of LabVIEW you are using.

LabVIEW FPGA was unable to contact the Compile Server at "localhost" on port 96.

Hi,
The following error occured when i am trying to compile my design on labview fpga 8.6, and the error reads as follows.
"LabVIEW FPGA was unable to contact the Compile Server at "localhost" on port 96. The server name or port may be incorrect, a firewall may be blocking communications with the server, or the configured timeout may be too low. You may reconfigure Compile Settings by clicking the Configure button or try contacting the Compile Server again by clicking the Retry button. Click the Cancel button to abort."
Can ane one help me in sorting out this error.,
Regards
KalyanSuman KV

This should solve it

LabView fpga VHDL code and compiler

Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.

Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer

How can I install (download) a Labview FPGA code onto Altera FPGA chip using Labview FPGA module?

Hi there
Guys i'm a very new labview user (PhD student), my project is about ( design and implementation of a high speed-yet sophisticated system using Labview environment then install this project's code (using Labview FPGA module) onto Altera-made FPGA chip).
so kindly, can any body help me in this?...is there any way to connect labview with Altera FPGA?...please anything would be said 'd be of great benifits
thanks a lot in advance.

as previously mentioned, labview fpga only supports national instruments targets utilizing xilinx fpgas. the hdl generated by labview fpga is encrypted and cannot be used to synthesize a design outside the labview fpga design flow.
however, if you must use labview for your project, it might be possible for you to design the system in labview and use one of the labview embedded modules ( http://www.ni.com/embedded )to generate c code which you can then port to systemc and compile for the altera fpga. i'm not saying it will be easy, but it should be possible.

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Labview FPGA called another software component

Hi
I am trying to compile my FPGA code which has previously compiled. I get this error.
"Labview FPGA called another software component, and that component returned the following error:
Error Code: -52009
NI Platform Services: The requested resource has been marked for deletion and is rejecting new requests."
What is this error code?

Hi,
I've been looking in to this for you today - unfortunately, that seems to be a really rare error code which doesn't come up very often on our systems, so there's no quick fix that I can find.
A couple of options:
1) Have you made any changes to the code recently, in terms of updating it from an earlier version of LabVIEW? If so, it may be worth mass compiling your project up to the latest version in case there are references to software components which no longer exist.
2) It's probably worth a try repairing your LabVIEW, FPGA and RIO drivers installations from disk, as described here: http://digital.ni.com/public.nsf/allkb/FE6B641E86E55AF2862576DE00038001?OpenDocument
This could be due to some kind of missing or corrupted component in, for example, the Xilinx Tools
3) Are you referencing any kind of external software, such as DLLs or third party instruments, in your file?
4) What hardware are you using?
Please let me know how you get on with these queries.
Best wishes,
Chiara A
Applications Engineer with NI UK & Ireland

Labview FPGA: Why not have local variable without indicator?

In Labview FPGA, to transfer data among parallel loops, there are three ways or maybe more, local variable, global variable and block memory. The problem with local variable is that it needs an indicator along with, not like global variable. I was thinking why Labview doesn't make a kind of local variable not need indicator? I guess local variable itself doesn't cost resource much compared to global variable, however when it comes into indicator, it will cost more. Just an idea, though. I guess there is a reason NI doesn't do that.

As in Labview document, global variable can be used for transfer data among VIs, which local variable isn't capable of.
Global variable is not always a better solution. From my experience, it is still unclear among different compilations using local vs global in terms of resources. A thread here http://forums.ni.com/t5/LabVIEW/FPGA-global-variables-vs-front-panel-items/td-p/1407282 talks about that too.
Stephen, is there any documents say that global makes timing worse? I didn't see this noticeable.

How to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.

how to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.
attachment:a sine signal using dds theory. Hope to get some help. Thanks!
Attachments:
FPGA DDS SineGen IP.vi ‏42 KB

you need to increment the "accumulator increment" during the duration of the chirp. the "accumulator increment" controls the frequency of the DDS cycle. by increasing it's value, you are increasing the frequency. the math for increment values follows the same math as determining the frequency to increment value.
Stu McFarlane
Viewpoint Systems, Inc.

LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)

Hello NI forums,
Question:
See the attached picture from a modified version of the LabVIEW DRAM FIFO example. It probably explains my question more effectively than the paragraphs below.
What is the difference to the LabVIEW / Xilinx compiliers, if any, between placing two independent branches of code in the same SCTL, versus placing them in individual SCTLs (in the same clock domain)?
Misc. comments:
I have briefly experimented with this concept using the included LabVIEW DRAM FIFO example (example finder >> Hardware Input and Output >> FlexRIO >> External Memory >> Simple External Memory FIFO.lvproj).
I compiled the default example (the read and write interfaces are in separate 40MHz SCTLs) five separate times. Then I put the read and write interfaces in the same 40MHz SCTL and compiled another five times. The result (when both read and write interfaces were in the same SCTL) was a reduction in resource usage (according to the compilation summary).
However, due to my lack of knowledge I'm hesitant to conclude that placing everything in one SCTL is always the best option. For example, I do not know what is created 'behind the scenes' with each SCTL. Perhaps putting independent branches of code in separate SCTLs makes it possible to route clock, reset, implicit enable, etc. signals more effectively.
Background information:
My task involves acquiring 2 channels of analog data using the NI 5772 and PXIe-7966. Data acquisition takes place in a 200MHz SCTL, and downstream processing is performed in a 100MHz SCTL.
During a vast majority of the 100MHz SCTL processing stages of the FPGA VI, the 2 channels of data do not interact with eachother. So it would be easy for me to place them in separate 100MHz loops if doing so would somehow help the design (timing, resource usage, etc.).
Thanks!
Attachments:
question.png ‏76 KB

Intaris
Trusted Enthusiast
Posts: 3,264
Re: LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
‎10-28-2014 12:11 PM
Just out of interest, what is the resource usage differential between the two versions?
In response to the above comment,
This is a little embarrassing, but it seems like the resource usage is similar than I initially thought for this particular example. I think the previous compilations that I based my assumption on coincidentally used more resources in the 2-SCTL loop case. I just compiled each version two additional times (see below).
Here's the version with everything in one loop:
Device Utilization
Total Slices: 17.6% (2587 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4855 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 16.9% (2493 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4858 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Here's the version with the read and write in separate loops:
Device Utilization
Total Slices: 16.4% (2407 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4852 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 19.4% (2859 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4859 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)

FlexRIO DRAM problem in Labview FPGA 2010

Hello,
I am just switching from Labview FPGA 2009 to Labview FPGA 2010 and I am having compilation problems with very simple projects that shouldn't fail to compile.
I am using a FlexRIO 7965R board as a target. Initially, I just wanted to recompile a project that was working fine under Labview FPGA 2009. When it failed, I drastically
simplified it to isolate the source of error. I ended up with what is attached. In this very simple VI I just write some values into DRAM banks in one timed loop, read them out in another and send them through a Target to Host DMA FIFO. Both loops are quite slow running at only 40 MHz. Previously, I was able to compile VIs with DRAM clip nodes in timed loops running at 100 MHz without any problems.
The compilation fails with this summary:
"Compilation
failed due to resource overmapping"
although it should fit easily.
The error is definitely related to DRAM. This s what Xilinx log says:
"ERRORlace:543
- This design does not fit into the number of slices available in this device
due to the complexity of
   the design and/or constraints.
   Unplaced instances by type:
     IDELAYCTRL    21 (48.8) "
Then it lists these instances (about 20):
   0. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate0
   1. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate1
   2. IDELAYCTRL Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate2
Both DRAM banks are configured with the clip node for 128-bit FIFO version v1.1.0. I also tried using the legacy version v1.0.0 but it didn't make any difference.
It looks like I have some configuration problems I can't identify or there is something wrong with the DRAM clip node in Labview FPGA 2010.
Any ideas on what could be happening here? Any help would be much appreciated.
Regards,
Ivan
Attachments:
flexrio_dram_test.lvproj ‏157 KB
flexrio_dram_test_fpga.vi ‏124 KB

Hello Ivan,
It looks like in your project you are using both the NI 5761 adapter module and DRAM. We have seen a few cases where certain combinations of DRAM, adapter modules, and FlexRIO FPGA targets in LabVIEW FPGA 2010 have caused some resource overmapping errors of the IODelayCtrl components used in the adapter module and DRAM CLIPs. Due to a bug, certain constraints inside of the CLIP cores are misinterpreted by the ISE compiler causing this overmap error when you switch to LabVIEW FPGA 2010.
This was reported to R&D (# 258076) for further investigation and to create a long term fix. In the meantime, for this specific issue please use the following knowledgebase article to apply a patch to your FlexRIO fixed logic files. This patch updates some of the constraints used by the DRAM to ensure that the Xilinx compiler can properly interpret them. There are more details on your issue in the knowledgebase as well.
Knowledgebase 5E4FNCDP: Error, “Compilation Failed Due to Resource Overmapping,” When Using NI FlexR...
If you do run into any other issues regarding IODelayCtrl components, feel free to reply to this forum topic to let me know about them.
Regards,
Browning G
FlexRIO R&D

Error in Compiling onto FPGA

When I try to compile my FPGA code generated from the FPGA wizard I get this error
An error occurred attempting to connect to this compile server.
Details:
LabVIEW: An exception occurred within the external code called by a Call Library Function Node. The exception might have corrupted the LabVIEW memory. Save any work to a new location and restart LabVIEW.
I already tried uninstalling and reinstalling xilinx

Labview 12.0
Xilinx 13_4
I've only attempted to compile code created by the wizard
Attachments:
Error Screenshot.JPG ‏160 KB
ni_support.zip ‏319 KB

Incremental Compile LabVIEW FPGA

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