Counter output PCI 6229

Hi all,
i have a little problem with NI pci 6229. I want generate a pulse train on both counter CTR 0 and CTR 1. I look the example that run on machine but i dont find the pin , with the oscilloscope, with y train pulse. I check the between Dgnd and PFI 8 ( pin2 ) but i dont see a train.
How can i solve ? What is the correct pin couter out on NI PCI 6229 ? it is referred to Dgnd?
tanks

Hi,
the terminal for a counter output task is PFI12 and not PFI8. The PFI 12 has the default Pin number 2.
NI PCI/PXI-6229
http://zone.ni.com/reference/en-XX/help/370466W-01/device_pinouts/6229_pinout/
Have a nice day.
Regards,
A.

Similar Messages

Counter problem PCI 6229

i am using TWO PCI 6229 cards (2*2 counters, DMA Channels), OS-winXP, LabVIEW 2009 SP1.
now using 3 counters (1. edge counter, 2 and 3 for semiperiod measurements).
i can run the edge counter alone without problem. but i cant run all the 3 counters in parallel.then the whole application slowsdown and i see the readVI at 3rd counter (buff_semi-period_continuous) not running.
i have changed the data trasfer mechanism from DMA to Interrupts but that also doesnt help.
analog input (16 differencial ) and output channels of both the cards are using.
can any one suggest a solution to this problem??
Kudos always welcome for helpful posts

Hi RENN,
the semi-period-measurement is a implicit-timed measurement. This means that there is no fixed point in time when the result of the measurement is delivered. (It depends on the signal when the driver provides you with a valid value.)
The behaviour you see is mostly caused by using multiple implicit-timed measurements in one single loop, esp. with buffered measurements.
To prevent this kind of deadlock use a single loop for every semi-period measurements.
I hope this helps.
Ralf N.

Counter Output Pin on PCI-6229

I am using NI-DAQmx 7.3 C API with (among others) a PCI-6229.
I have used DAQmxSetCOPulseTerm() to connect a counter output to a terminal other than the default. It seems to work- the output pulses do, in fact, appear at PFI 6 (the terminal I'm using for testing). But the pulses continue to appear at the default output pin as well.
Is that expected?
In order to reverse the situation, I used DAQmxResetCOPulseTerm() just before calling DAQmxClearTask(). The function returns zero, but if I subsequently make a new task to do pulse output from the same counter, pulses appear at both PFI 6 and at the default pin.
Am I missing something?
John Weeks
WaveMetrics, Inc.
Phone (503) 620-3001
Fax (503) 620-6754
www.wavemetrics.com

Salvador Santolucito wrote:
Hi John,
I would suggest using the DAQmxTristateOutputTerminal. I have tried what you are doing in LabVIEW and I'm seeing the exact same results. When I set the default pin to tristate, the counter output does not show up on it.
-Sal
Thanks for trying it and confirming what I saw, and thanks for the pointer to DAQmxTristateOutputTerminal.
John Weeks
WaveMetrics, Inc.
Phone (503) 620-3001
Fax (503) 620-6754
www.wavemetrics.com

PCI-6229 M-Series (count 3 encoders)

Hello,
I only have one DAQ board (PCI-6229 M-Series) and as I know, the board have two counters:
Ctr0 which uses PFI8 and PFI10 - now using that to count outputs from my first encoder
Ctr1 which uses PFI3 and PFI11 - for my second encoder
But I have 3 encoders, can I use other PFI pins on the DAQ board to count the outputs coming from my third encoder? Is it possible with just one DAQ board? Did I miss any example code which tell me how to do this?
Thanks alot.
Kenneth

Hi
Try the link below
http://sine.ni.com/apps/we/niepd_web_display.display_epd4?p_guid=F0F64AEE06C0010CE0340003BA7CCD71&p_...
for using a counter as the DIO clock for M Series boards.
Requirements= LabVIEW 7.1
NI DAQ MX 7.3
I hope this example helps!
Kind Regards,
Kurt
Attachments:
Using_a_Counter_as_the_DIO_clock_for_M_Series.vi ‏84 KB

How can i output a voltage on PCI-6229 port with visual basic 6 ?

Hello,
PCI-6229 card is using DAQmx, that not support VB 6 officially.
However, members of this forum found out a way to write/read on digital port with vb6 and DAQmx.
This was working well for me indeed.
Then, i wanted to output a voltage on AO. I followed the same procedure they used for DI/DO but in vain.
Apparently, the function DAQmxCreateAOVoltageChan()* causes trouble.
Using the .exe of the program, i get this error :
"error -200077 : Requested value is not a supported value for this property."
Thank you for any ideas that can sort this out.
* Public Declare Function DAQmxCreateAOVoltageChan Lib "nicaiu.dll" (ByVal TaskHandle As Long, ByVal lines As String, ByVal nameToAssignToLines As String, ByVal min As Single, ByVal max As Single, ByVal units As DAQmxUnits, ByVal customScaleName As String) As Long
call : DAQmxErrChk DAQmxCreateAOVoltageChan(TaskAnalog, txtChanAnalog.Text, "", Min, Max, DAQmx_Val_Volts, 0)

Hello,
What is your buffer size ? The buffer should be 0 or greater than 2. You can get this error if your buffer size is equal to 1.
Regards,
Isabelle
National Instruments France
Isabelle
Ingénieur d'applications
National Instruments France

Continuous in- and output with PCI-6229

Hi All,
I'm currently evaluating a PCI-6229 card on RTX (and maybe InTime later on). The main goal of the evaluation is to prove we can get hard real-time, deterministic behaviour from this system in order to use it to replace our current DSP-based solution.
To do so, I'm setting up a rather simple program that should
- continuously acquire 1 channel @ 20kHz
- have a processing loop of 5mSec, ie 100 samples; this loop should be entered every 5mSec as exactly as possible
- do some simple processing in the loop (thresholding the signal)
- bring out the result on an analog output (low signal if signal is under threshold, high signal for all samples above the threshold)
I could get the basics working pretty quickly: continuous input, continous output, continuous input with dma, input using interrupts.
Trying to combine everything isn't really working out however.. Normally I'd try and try until knowing the device inside-out but now I have a rather strict timeframe so hopefully someone here can provide some insight.
Questions:
1. For the input, I can get an SC_TC interrupt each time one frame is scanned. I measured this on a scope by toggling a digital output on the card, and there's no noticable jitter on the squarewave which is a good sign.
However I'd like to combine this with DMA, but the DMA is lagging a bit on the interrupt so I end up having to poll the DMA after all in the ISR, so there's no use using the interrupt in the first place.
Is there a way to set up continuous DMA servicing and get an interrupt from the DMA system itself after 100 samples are transferred?
2. For the output, I cannot get continuous mode working with DMA, only by writing to the FIFO manually. I can preload a couple of frames with the dma, but after calling aoStart(), tDMAChannel::write() works once, but all calls afterwards return kBufferUnderflow. Any ideas?
I probably have to check when exactly to write to the DMA, but I have no idea which of the many status functions to use. Tried with AO_Status_1.readAO_FIFO_Half_Full_St() but that's not it. tried to write it on each UC_TC interrupt but that didn't work either.
3. DMA is, to my understanding, a more performant way of getting samples into the host and doesn't require to call AI_FIFO_Data.readRegister() in a loop and vice-versa for the output side. But are there really benefits in using DMA?
4. I made a basic program to bring everything together the simplest way possible: preload 100 samples in the output FIFO, start analog input, start analog output, have the ISR copy all values directly from input to output FIFO.
Putting both analog signals on a scope, I expected to see the input and about (see question5) 5mSec later the same signal on the output, with no jitter.
However what I see is the output is just floating around, in other words there is no fixed delay between output and input! How is this possible? I use the same divisor for in-and output. Is there any sample code available that achieves what I want?
5. Is there a way to start both input and output at the exact same time, eg at the same edge of a certain clock pulse? How are input and output synchronized? Can I be sure they never go out of sync?
Solved!
Go to Solution.

update: looking at the DAQmx control samples, it seems some of them set the start trigger for the AO to the AI start trigger. I mimicked this using kAO_START1_SelectAI_START_1 with the aoTrigger method, and the sync seems better now: the output starts exactly 10mSec after the input (or 5, if I preload only one frame) and stays in sync for about 25mSec. That it goes wrong.
At the moment I'm using no DMA, just one simple interrupt routine that basically does
board->Interrupt_A_Ack.writeAI_SC_TC_Interrupt_Ack( 1 );
board->Interrupt_A_Ack.flush();
toggle ^= 1;
board->Static_Digital_Output.writeRegister( toggle ? 0x00 : 0xff );
for( u32 i = 0 ; i < numSamples ; ++i )
const u32 val = board->AI_FIFO_Data.readRegister();
board->AO_FIFO_Data.writeRegister( val );
In the screenshot in the attachment you can see this goes wrong: cursor A shows the position of the input signal (=AI 0, yellow) that should be shown 10mSec later at the output (blue line=AO). Cursor B shows this 10mSec later position, and you can see there's some garbage right after the cursor. This is the data that was written to the AO FIFO in the fifth interrupt (interrupt position show in purple).
Trying to figure out where that comes from, I put board->AI_Status_1.readAI_FIFO_Empty_St() in the interrupt loop. And effectively, when trying to read the 500th sample, it reports that the FIFO is empty. Consequently the data written to the AO FIFO does not make sense anymore. But I do not understand how can this ever happen? The SC_TC interrupt is fired whenever 100 samples are read from the input. So after this interrupt occurs, the FIFO should always contain at least 100 samples, no?
Attachments:
tek00000.png ‏22 KB

6229 counter output inhibit

Greetings all,
I am trying to use my pci-6229 board and BNC-2090a for the following purpose.
I want to monitor analog votages on AI0-x while putting out a ttl signal at lets say 60Hz.
If an analog signal goes above a certian value I want to stop the counter ttl trigger, or possible
lower the rate, to maybe 10Hz.
The main concern is monitoring the voltages at the fastest update rate and being able to immediately turn off the
outgoing counter or change its rate. By changing the "# of Samples per Channel" the update rate seems to change, but I'm not sure
how to optimize this.
Any suggestions, I've searched the boards but am having some difficulties.
Thanks,
Jim
Message Edited by xband on 01-29-2008 03:26 PM
Attachments:
ReadBNC-2090a1.vi ‏26 KB

Ok, I have made an attempt at doing what I would like using a Pause Trigger, I can make my digital state go to high by putting >1V on AI0.
The counter rate does not change though.
I'm also not sure of how to "Clear" the counter task, whenever I wire to a "Clear Task" outside the loop, it gives an error.
Jim
Message Edited by xband on 01-29-2008 07:56 PM
Attachments:
ReadBNC-2090a Pause Trigger1.vi ‏52 KB

How do I use a quadrature encoder as an external clock (PCI 6229)

Hello, ( a similar post has been placed on DAQ forum apologies as I did not know best place)
I have a PCI 6229 M Series data acquisition card. I want to use a quadrature encoder to be the external clock driving the acquisition of a number of signals. I have set up reading 24 signals each time a clock pulse is received using the DAQ assistant and set my external clock to pin pfi8 (I think) this is then connected to an encoder output. This works well enough until the encoder is run too fast when it appears I am either missing pulses or getting bounce.
How can I set up to clock using a quadrature encoder? I have seen a number of questions on this forum regarding quadrature encoders and reverse counting but not on using them as an external clock.
Basically I want to have the stability and "bounceless" nature of using two outputs from a quadrature encoder whilst still using an external clock. Is this just a case of configuring controls to certain pfi's? If so how is it done?
Any help or pointers would be helpful. So far I have managed very nicely by simply using the DAQ assistant and the interface it has would suggest that if configured for a certain pfi pin I could actually still use it.
Thanks in advance.
Kevin

Hi,
Well I've had alook into this for you and I'm not quite sure I understand what you are looking for.
Is it possible for you to phone back in to support?
The reason you are seeing bounce at high speeds, or indeed loss of points, is due to the sampling rate that you have set up.
What you will find is that the trigger will start an aquisition of a number of points at a certain rate. If your sampling rate is too low then you will not finish that sample batch before the next set of samples is recorded.
It is possible to use an external clock into a trigger or digital line, however this will limit the number of samples you can take to the speed of your encoder.
If you increase your sampling rates, and then configure a start trigger from a single input from the encoder you will be able to record a number of samples after a rising/falling edge. (Set the clock as an internal clock)
Hope this helps
AdamB
Applications Engineering Team Leader | National Instruments | UK & Ireland

Can I generate pulse trains on more than one counter output at the same time?

I have a PCI 6601 card with a BNC 2121 to connect the signals to two devices. The card is used as a trigger for both devices and I want to be able to generate pulse trains on two output channels at the same time, with a time delay between the two. How do I do that in Labview 7.1 Development with DAQmx?

I feel foolish for not being able to figure this out, but it still doesn't work. Attached is the VI I use now. Counter 0 generates a finite pulse train and I programmed Counter 1 to generate a retriggerable single pulse triggered by CtrOinternaloutput. I still get the same error message: -50103 The specified resource is reserved. The operation could not be completed as specified.
The same happens if I set the trigger for counter 1 at PFI36 (default output of counter 0) or any other PFI line. If I try a pulse train generation on only one of the counters, both work fine.
If I try the example in traditional DAQ for multiple counter outputs with phase delay, it works fine.
Can you tell me what I'm doing wrong?
Attachments:
Shutter_AND_lamp_trigger.vi ‏103 KB

How to check 6 digital signals change value at the same time with PCI-6229??

I am using DAQ card PCI-6229.
Channel 1 generate a digital signal.
Channel 2,3,4,5,6,7 acquire digital signals.
I want to check:
1. Whether the rising edge of Channel 2,3,4,5,6,7 occures at the same time;
2. The time delay from the rising edge of Channel 1 to the rising edge of Channel 2,3,4,5,6,7 is within a certain range.
I know I can use counter to get the two edge seperation time delay. But I only have two counter, it is two time-consuming if I check one by one.
I don't know how to check the rising edge of 6 different channels occure at the same time.
Does anyone has any suggestions?
Thanks

Hello,
You can use the DAQ card's digital input change detection circuitry to detect changes in the input, you can then use a counter to measure the relative time between samples. Please read Page 6-9 DI Change Detection Applications for more information. Let me know if this helps
Christian A
National Instruments
Applications Engineer

Counter Output/Counter Input PXI Signals Behaving Erratically

Question for all your LabVIEW guru's out there,
I am running a frequency loopback test using the NI PXI 6229 MIO DAQ card. I am generating a "Counter Output" pulse train signal which feeds through my device under test and then back out of my device under test and back into the PXI 6229 for a "Counter Input" frequency measurement. Both the "Counter Output" and the "Counter Input" are assigned different PFI lines using DAQmx in LabVIEW.
I have 4 lines to test on my DUT. All four lines run this same frequency measurement but with different PFI lines on the PXI 6229. Each line is test independently.
This is my setup for the 4 lines:
Path 1: P2.0 (Counter Output - Pulse Train) -> DUT (Device Under Test) -> P2.1 (Counter Input - Frequency Measurement)
Path 2: P2.2 (Counter Output - Pulse Train) -> DUT (Device Under Test) -> P2.3 (Counter Input - Frequency Measurement)
Path 3: P2.4 (Counter Output - Pulse Train) -> DUT (Device Under Test) -> P2.5 (Counter Input - Frequency Measurement)
Path 4: P2.6 (Counter Output - Pulse Train) -> DUT (Device Under Test) -> P2.7 (Counter Input - Frequency Measurement)
where:
P2.0 = PFI8
P2.1 = PFI9
P2.2 = PFI10
P2.3 = PFI11
P2.4 = PFI12
P2.5 = PFI13
P2.6 = PFI14
P2.7 = PFI15
I have a LabVIEW VI which generates the "Counter Output" and reads the "Counter Input" frequency. I am seeing weird behavior from the PXI 6229 card. I can test "Path 1" and "Path 2" and the frequency I read is what I generated. No issue there. However, when I test "Path 3" and "Path 4" the frequency measurement is erratic. The readings are two different frequencies repeated over and over again and none of those frequencies are the expected frequency which was generated out of the "Counter Output." If I reset the card, and start by testing "Path 3" and "Path 4" the frequency readings are correct and the erratic behavior is gone. However, when I try to then test "Path 2" and "Path 1" now those lines have the erratic frequency issue. I can continue resetting the card and see same issue. The PFI lines that I test first will always pass.
To summarize:
Steps Taken:
1. Test Path 1 = SUCCESS
2. Test Path 2 = SUCCESS
3. Test Path 3 = Erratic Frequency (Two Frequencies repeated over and over again in my frequency results array)
4. Test Path 4 = Erratic Frequency (Two Frequencies repeated over and over again in my frequency results array)
5. Reset the PXI 6229 Card
6. Test Path 3 = SUCCESS
7. Test Path 4 = SUCCESS
8. Test Path 3 = Erratic Frequency (Two Frequencies repeated over and over again in my frequency results array)
9. Test Path 4 = Erratic Frequency (Two Frequencies repeated over and over again in my frequency results array)
I am wondering if Port 2 (P2.0-P2.7) on the 6229 card has certain dependecies and this is why I am seeing issues. I am trying to get around this issue so that I don't have to always reset the card.
Are P2.0-P2.3 (PFI8-PFI11) and P2.4-P2.7 (PFI12-PFI15) treated differently or require different setup? How do I resolve this issue?
Thanks so much!

I have a theory...
The DAQ card follows a policy called "lazy uncommit" wherein the terminal used for the output will continue to be connected to the counter even after the task has completed (until the terminal is needed for something else). So as you run more tests, the counter output will end up driving more lines. This behavior should be easy enough to confirm.
As the DAQ card drives more lines, I'd imagine this affects the actual signal. You could scope it to check, but it sounds like either the rise/fall times are becoming longer or some extra noise is being introduced on the line.
The readings are two different frequencies repeated over and over again and none of those frequencies are the expected frequency which was generated out of the "Counter Output."
This implies you are picking up an extra edge during transitions--this isn't too uncommon if the signal is noisy since there is no built-in hysteresis on the DAQ card. I would expect the measured frequencies to have periods that sum to either the full period or the semi-period of your actual signal (depending on how many duplicate edges are detected).
Suggestions are as follows:
To stop the DAQ card from driving multiple PFI lines, it would probably be easiest to just programmatically reset the device in between your tests (using DAQmx Reset Device). If you can't reset the device (e.g. because you are running some other task that can't be interrupted) then you can instead configure a dummy task that uses the PFI line in question as an input.
To stop the DAQ card from picking up multiple edges during transitions, you should configure a digital filter on the input terminals. If you reset the device it sounds like this might not be necessary... it's up to you if you want to configure this or not.
Best Regards,
John Passiak

How to filter starttrigger on counter output precisely

HW PCI6602
Measurement studio 2008 (C#)NI-DAQmx 9.02I’m trying to trig a camera using the output from a counter.
The camera should be trigged when the counter input pulse width is larger than approx (filterPulseWidth 10us).To do this a have set up the following tasktask.COChannels.CreatePulseChannelTime(counter, "TriggerTaskChannel", COPulseTimeUnits.Seconds, COPulseIdleState.Low, 0, 80E-6, 0.007); task.Triggers.StartTrigger.Type = StartTriggerType.DigitalEdge; task.Triggers.StartTrigger.DigitalEdge.Edge = DigitalEdgeStartTriggerEdge.Rising; task.Triggers.StartTrigger.Retriggerable = true;task.Triggers.StartTrigger.DigitalEdge.DigitalFilterMinimumPulseWidth = filterPulseWidth; task.Triggers.StartTrigger.DigitalEdge.DigitalFilterEnable = true;Unfortunatly this filter has the following behaviour”If the period of the filter clock timebase is tfltrclk, this filter guarantees topass pulse widths that are 2*tfltrclk or longer and to block pulse widths thatare tfltrclk or shorter. A pulse with a width between these two ranges may ormay not pass, depending on the phase of the pulse with respect to the filterclock timebase”.It means that I have no sharp distinction on my filter as one would when applying a filter to an ordinary pulse width measuring task. Implementing this with via the software in a callback is to slow.The bottom line is that I would like to generate a pulse on my counter output when the trigger/counter input is greater than say 10us. The output pulse could be predetermind as in the sample code above or as long as the filtered input (I.e counter just pass filtered input to my output).How can this be done? BR
Jongas
Solved!
Go to Solution.

Hi Jongas,
Is it OK if the trigger is sent once the pulse hits 10 us, rather than
on the exact falling edge? I'll assume the exact timing isn't as important, but you would like the trigger to occur very close to the falling edge (within a couple of us). The important thing is that we trigger as close as possible to when the PWM has hit 50% duty cycle.
Some brainstorming:
Digital Filtering on the 660x Isn't the Best for This:
Digital filtering might not be as practical here on your 6602 due to the region of uncertainty between 5 and 10 (or 10 and 20) us pulses. The TIO boards count two consecutive edges of a filter clock to determine when to pass a signal through so the guaranteed rejected pulse width is always half of your guaranteed passed pulse width (providing an external filter clock timebase that is synchronized with your external signal could potentially reduce this uncertainty but I honestly haven't tried this before and I would imagine it is not going to be very straightforward).
X Series Alternative:
Our X Series devices use a different method of digital filtering that would work better for you. If a hardware change is an option (and you can use PCIe) then you might consider this. You could use the 20 MHz timebase as your filter clock timebase and could guarantee to pass 10 us (200/20M) and reject 9.95 us (201/20M). The 6320 is currently our lowest cost X Series board. A couple of points about this solution:
1. To configure the PFI filter, you need to use some sort of dummy task to
access the property nodes. Here is an
example of this (although it is written in LabVIEW).
2. You can route the filtered PFI signal to be exported on another PFI line, but this will reserve Counter 3. This is documented in the Device Routes tab of Measurement and Automation Explorer.
3. The filtered output will be 9.95-10 us delayed from the input signal, so you could trigger the camera off of the rising edge of the filtered output directly and be fairly close to the actual falling edge.
External AND Gate Alternative:
You could configure a Counter Output to generate a re-triggerable pulse with a 10 us initial delay (to be triggered off of the rising edge of your PWM signal). Assuming the pulse is short enough to complete before the next period of your PWM signal, the counter output would only be high at the same time as the PWM signal if the signal was longer than 10 us. Use the external AND gate to combine these two signals and the result would be the trigger for your camera (the rising edge would correspond to 10 us after the PWM signal first goes high).
If you wanted to you could make the counter output pulse a little longer (say 8 us) and trigger the camera off of the falling edge out of the AND gate (a.k.a. rising edge out of a NAND gate) which would line up with the exact falling edge of the PWM signal. Don't make the CO pulse too long or it will overlap with the next period of the PWM.
Another Idea:
One idea that I keep coming back to is to use the internal rollover event of a counter input task (a pulse is generated whenever a counter rolls over on its Internal Output which can be routed to a PFI line). I don't think this will work, but the idea in theory would be to:
1. Set Default state to known value (e.g. 2^32-200).
2. Gate the Counter so it only counts during the time PWM is high. Have it count the 20 MHz timebase.
3. Reset the Counter to default state on the falling edge of the PWM signal.
4. The counter would rollover if 200 pulses occurred of the 20 MHz timebase (10 us), and the Counter Output could be routed to a PFI line to trigger the camera.
The problem is that there is no good way to reset the counter except for an encoder measurement (Kevin has already made a nice suggestion about this). A Pulse Width Measurement would technically reset the counter, but you cannot currently set the default value of a Pulse Width Measurement task so there is no way to make the rollover happen prematurely).
Configuring an encoder measurement and working with the multiple counters on the 6602 to produce appropriate A,B, and Z signals might be a method to look into further, but at this point I think you'd be better off with an external AND gate.
I don't want to say it's impossible with just the 6602, but I can't think of a straightforward way to go about it without external hardware (although maybe I can sleep on it and think of something later... how many counters do you have to work with?).
With your current NI Hardware, I think your best bet is to go with an external AND gate. If you're planning on purchasing an X Series card the digital filtering idea is actually not a bad way to go.
I hope this is helpful!
Best Regards,
John Passiak

How does the PCI-6229 DAQ-card communicate with CB-68LP connector block?

Hello!
I want to do a very simple task which is to just turn on/off a LED. I am using LabVIEW 7.1 and I have a DAQ-card PCI-6229. The DAQ-card is then wired to a connector block CB-68LP.
Now my problem is to figure out how the connector block communicates with the DAQ-card?
In the file I attached there is a picture of connector block and the device pinouts from the DAQ-card. But how do I know which of pinouts triggers some connector on the connectorblock?
Which are digital outputs on the DAQ-card?
Where can I read about this?
Attachments:
daqANDconnectorblock.bmp ‏2437 KB

Hello asc01001:
The digital pins of the PCI-6229 are labelled as Px.y, where x is the port name while y is the channel name. For example, pin52 of the NI 6229 is P0.0; which is also port 0, channel 0 of the digital I/O of the DAQ card.
While "D GND", which are located at pin53, pin18, pin50, etc. are the negative terminal of all digital I/O of the DAQ cards.
Please advice if this helps.

Display counter output on graph

I have two counters generating continuous digial pulse trains from my PCI 6010, and I'm trying to display the output on a graph. I've got the output of one counter connected to an AI line that leads to a waveform graph, but I can't get anything on the graph. I've measured the output via external means, so I know the counters are generating the appropriate pulses.
Eventually I'd like to have some sort of indicator for each counter that indicates whether the counter is in the 'on' or 'off' state, but I figured getting the counter outputs to diplay on a graph would be a good first step.
My VI is below; the display part that isn't working is at the bottom of the case structure.
Thanks.

Once your code goes into the inner while loop your graph will never be updated since it will only execute one time. In order to update the graph continually you will need a parallel which handles the graph updates. A good way to pass data between the parallel tasks is a queue.
Mark Yedinak
"Does anyone know where the love of God goes when the waves turn the minutes to hours?"
Wreck of the Edmund Fitzgerald - Gordon Lightfoot

PCI-6229 Digital I/O sample clock problem

Hi,
I am using PCI-6229. I need to use digital output channel to generate 20KHz 30%duty cycle pulses.
The datasheet shows DO sample clock frequency can be 1M Hz. But in may application, only 100KHzTimebase can work to generate. But acctually I need at least 200K Hz.
Attached is the Vi I made. Can anyone help me with this problem?
Thanks
Solved!
Go to Solution.
Attachments:
Digital pulse_DO Channel.vi ‏26 KB

Hello All,
I tried to modify the VI posted in this thread in order to aquire a digital signal with the PCI-6229. Sinc the frequency of the signal is below 1k i tried to devide the signal of ctr0 respectively of freqout by 8 or 16 since 6.25k or 12.5k sampling frequency would be more than enough for my purpose. By the way, when I am using the 100k timebase for the timing of the task the programm is working. Since i try to monitor up to 20 channels, the amount of data genereated is too much. Therefore I tried to use the modified VI.
Sometimes, the VI works, but almost always, the DAQmx - Read VI doesn´t terminate.
Has anybody an idea what i did wrong?
Thank you for your assistance.
Sincerely,
Mirko
Attachments:
Digital pulse_DI Channel-1_mod.vi ‏32 KB

Counter output PCI 6229

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