Counters gating

I would like to generate two sets of pulse trains with my available counters (2): CTR0 is finite of about 50 pulses at 100Hz 80% duty cycle and CTR1 is continuous 40KHz and 50% duty cycle. I would like to internally connect the output of CTR0 to the gate of CTR1. The net effect is that I would get a 40KHz 50% signal for about 8ms and off for 2ms, repeat for 50 pulses.
After a couple hours of googling I found out that this not possible because labview use both counters to generate a finite pulse train.
Is this a show stopper? Is there someway to do what I described above in labview?
I am using labview 8.5 with PCI6221 card.
Thanks in advance
hv

Hi HV,
I would like to add a few things to my previous post. There is a way to do what you want to do with the PCI-6221. The approach you need to take will be a little different. Take a look at:
Creating a Delayed, Retriggerable and Finite Pulse Generator
Using One Counter to Generate a Retriggerable Finite Digital Pulse Train with a PCI-6602 and DAQmx
Retrigger and Repeat Finite Digital Pulse Train in LabVIEW
Let me know if you have any questions for me.
Best Regards,
Jignesh

Similar Messages

"Data Samples Overwritten before being Read" Error?

I have been working on this issue for over 3 weeks, I am getting an overflow error (Data overwritten before read), and I can't seem to get rid of it. I tried sevral suggestions, but still can't get rid of it. I am using two counters Gated by PFI7 and PFI4 to measure RPM. Ctr1 is Once Per Rev counter, and Ctr0 reads time reference at every edge. In our application, we average RPM after certain # of Revs, say every 100 Revs, we average them and we get an RPM reading. But the problem is before the averaging, the buffer seems to occur with speed exceeding 1000 RPM which is not nearly close to what we are looking for. I am using 16E-4 series and it supposed to handle high RPM ( I am looking for RPM at around 5000. I appreciate any feedback or suggestions on this issue, or a way may be I can handle the buffer to make it stop overflowing. Here is a snipet of the code:
DAQmxErrChk (DAQmxCreateTask("Counter Task1",&taskHandle[1]));
DAQmxErrChk (DAQmxCreateCICountEdgesChan(taskHandle[1],"Dev1/ctr0","Counter0",DAQmx_Val_Falling,0,DAQmx_Val_CountUp)); // Counter 0
DAQmxErrChk (DAQmxSetCICountEdgesTerm(taskHandle[1],"Dev1/Ctr0","/Dev1/20MHzTimebase")); // Sets 20MHz as source clock
DAQmxErrChk (DAQmxCfgSampClkTiming(taskHandle[1],"/Dev1/PFI7",40000,DAQmx_Val_Rising,DAQmx_Val_ContSamps,10000)); // using PFI7 as gate
DAQmxErrChk (DAQmxCreateTask("Counter Task2",&taskHandle[2]));
DAQmxErrChk (DAQmxCreateCICountEdgesChan(taskHandle[2],"Dev1/ctr1","Counter1",DAQmx_Val_Falling,0,DAQmx_Val_CountUp)); // Counter 1
DAQmxErrChk (DAQmxSetCICountEdgesTerm(taskHandle[2],"Dev1/Ctr1","/Dev1/20MHzTimebase")); // Sets 20MHz as source clock
DAQmxErrChk (DAQmxCfgSampClkTiming(taskHandle[2],"/Dev1/PFI4",40000,DAQmx_Val_Rising,DAQmx_Val_ContSamps,10000)); // using PFI4 as gate
DAQmxErrChk (DAQmxStartTask(taskHandle[1]));
DAQmxErrChk (DAQmxStartTask(taskHandle[2]));
DAQmxErrChk (DAQmxReadCounterU32(taskHandle[1],360*RevsToAverage,TimeOut,TimeBuffer,BufferSize,&NumberReadOnTimeCounter,NULL));
DAQmxErrChk (DAQmxReadCounterU32(taskHandle[2],RevsToAverage,TimeOut,OncePerRevBuffer,BufferSize,&NumberReadOnOncePerRevCounter,NULL));
Reading Counter0 is producing BufferOverflow error, I did try doubling the BufferSize even 4X, it didn't help. So, I making the buffer for 72000 samples for example, so it gets the 72000 samples requested in the first iteration of the loop, but when it comes in the next iteration, I don't think the buffer is empty. I do free up the memory on the way out from each iteration too, I am wondering if there is any addiotional housekeeping that I have to dod for the buffer, as I thought NIDAQmx takes care of the flushing.
Thanks for your feedback

Hi NewBe,
Thank you for posting on the National Instruments forums.
Is this the code that you are using in your application? One thing that I see off hand is that you are setting up and starting the task, then reading channels, but there is not stop or clear. Do you have a loop around your read section of code? You should not be configuring or starting the task after you do your read. If you want to do that, then make sure you have a close or clear task, depending on if you want to restart the task or reconfigure the task.
Another thing you can try is to for the numSampsPerChan to -1, which reads all of the data from the buffer each time you call the read function. If that fixes your issue, then it means that you are not reading off of the buffer fast enough so it fills up and you get that overflow error.
Please let me know what you find after trying this.
Thank You,
Nick F.
Applications Engineer

How do I output a finite pulse train through multiple counters?

Hello,
I have used LabView examples to create a VI to use with my TIO 6602 that generates a finite pulse train with varying duty cycle, frequency, number of pulse, and initial delay. I can also have it output the pulses through multiple counter channels, but all the channels have the same delay, and are output at the same time. I need each channel to have a specific delay from the first one.
In my VI, I use DAQmx to create a retriggerable finite pulse train by gating a counter with another counter. I have all the neccessary controls over the pulse train, but I can not seem to find an easy way to just copy this waveform and output delayed versions of it to other channels. The delay is very important because these signals will be used to drive ultrasound transducers in a linear array, and for the waveforms to focus at one point, the signal driving the transducers with a shorter distance from the focal point need a larger delay, so that the same waveform arrives from each transducer at the same time.
Any help with how I might do this would be much appreciated.
Thanks!

Hey Sneaky,
Here's a screenshot of the code I put together on how to use multiple counters. Also, take a look here for more information on how to sync multiple counters.
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:38 AM
-John Sullivan
Analog Engineer
Attachments:
4xcount.jpg ‏67 KB

How can one counter be sources (or gated) with the output of the other?

I'm trying to use the counters to generate a square pulse train that contains a certain number of pulses (on 6036E). For that I need to gate counter0 with the output of counter1. The manual seems to indicate that I need to use
GPCTR_Change_Parameter (deviceNumber, ND_COUNTER_0, ND_GATE, ND_COUNTER_1) ,
however it makes no difference to the output; I see no gating. What am I doing wrong? Am I missing something?
I would also like to source counter1 with the output of counter0. There's a similar function call to choose the source signal, but so far I've been unable to source a counter with anything but the internal timer. I guess the reason for it might be the same as the gating problem.
Petro

Hi Petro-
This example shows how to output a finite gated pulse train on an E Series board. It mentions that it is a CVI example, but the main .c file does not include any CVI-specific functionality so it should work if you're using ANSI C.
Equivalent functionality is available in NI-DAQmx for your board and is considerably more intuitive. An example of pause-triggered pulse train generation is available in the "C:\Program Files\National Instruments\NI-DAQ\Examples\DAQmx ANSI C\Counter\Generate Pulse\Dig Pulse Train Cont-Pause Trig" directory of your local drive. One method to generate the "pause trigger" pulse train is shown in "C:\Program Files\National Instruments\NI-DAQ\Examples\DAQmx ANSI C\Counter\Generate Pulse\Dig Pulse Train-Cont" .
I'm not sure what you mean when you say "I would also like to source counter1 with the output of counter0." What do you need to perform this operation for? The reliance of counter 1 on counter 0 and counter 0 on counter 1 creates a type of circular reference that is almost guaranteed to be problematic.
Hopefully this helps-
Tom W
National Instruments

Simuntaneous arming of counters

Hey guys,
I am trying to configure seven counters on a PCI6602 to simulate a quadrature encoder signal(Channels A,A',B,B',Z,Z') and a regular encoder signal(Channel X). The quad encoder signal works fine and was done by setting up Pulse Train Generation on channel A, and Retriggerable pulse generation on the other 5 channels. I then use channel A as the gating signal for the other 5 channels. This works beautifully! Now I am stuck though. To generate a regular encoder signal, I need to output a pulse train that starts on the same rising edge as channel A (with no delay!), but has twice the frequency of channel A. I have tried triggered pluse train generation (too much delay in Channel X), and retriggerable pulse generation(can't g
et a frequency that is twice that of channel A)with no success. Has anyone got any suggestions? I am using the latest version of NIDAQ (6.9.3) with MS Visual Basic (no CW components) on a PCI 6602 counter board.
Thanks,
Dave

Dave,
Given that you know the frequency of A, so you can specify it's double for X, we can try and do the following ...
Set up the pulse generation on X to be reverse (negative) polarity. Then setup X to be armed by a rising edge hardware trigger (triggered pulse generation). Use A to trigger X. Since you are using reverse polarity for X, and the width will come before the delay of the pulse, then the X train will start when the A train starts. The only delay you will have is a slight, and unpreventable, hardware delay, in the nanosecond range.
Without using reverse polarity, the delay would come before the width, and you would notice a large delay, which depending on your frequency and duty cycle, could be too large.
Regards,
Justin Britten
Applications Engineer
National Instruments

Want to trigger event count from both counters (E) to buffer using FOUT (100kHz/16 or slower) as a trigger

We are using a AT-MIO-16E-1 board. We would like to run an xy raster pattern from the buffer (AO) in order to reduce scan times (256 x 256 pt images). At each AO (voltage) point we would like to read from both onboard counters and store the number of events counted to memory, reading out the buffer say every 256 pts (1 scan line). In order to ensure accurate counting periods the counters need to be triggered to coincide with some "dwell time" at each AO voltage pt. We have thought of using FOUT for the trigger or perhaps out analog out scanning signal but are concerned that the FOUT freq is too high (6250 khz - we would like 100hz-10khz). Any suggestions or e
xamples would be appreciated.

Hello;
The main problem there is going to be the counter triggering. I'm saying that because, there isn't a way for the Analog Input operation to send pulses that will trigger of the timer operation at multiple voltage levels. The only solution for this I can think of is, instead of having an analog voltage level which would indicate the position of xy, if you could have a device which would give a TTL pulse instead when the desired position is reached, then you could use the 6601 to have a triggered operation at the counter. Another constraint for your application right now is the fact that the E-series boards' counters don't have triggering features, only gated features.
Anyway, you would need to have a TTL pulse either to trigger (in case of the 6601 count
ers) or to gate (in case of the E-series board), when the desired XY position is reached.
Meanwhile, you can refer to the Labview examples for Streaming to disk, Analog I/O and counter operations. You can go to Search Examples->I/O Interfaces->Data Acquisition->Data Logger ( for streaming to disk operations); Search Examples->I/O Interfaces->Data Acquisition->Analog Output ( for Analog Output Operations); and Search Examples->I/O Interfaces->Data Acquisition->Counters (for counter operations). Also; I'm including an Application Note which talks about synchronization of multiple DAQ tasks I think will be helpful for you also.
Regards.
Filipe
Attachments:
Advanced_Sync_Techniques_for_DAQ.pdf ‏189 KB

Rajouter le nombre d'implulsion sur l'exemple "Multiple Counters with Phase Shifts.llb"fournit par NI

Bonjour,
J'utilise une carte PCI6601 NI DAQ traditionnel avec LV6 et je génère 4 signaux à l'aide de "Multiple Counters with Phase Shifts.llb"fournit par NI. Cela marche très bien néanmoins je voudrais pouvoir rajouter le nombre d'impulsion. Ce nombre serait le même pour les 4 signaux.
Merci d'avance

Monsieur,
Dans cet exemple vous ne pouvez fixer le nombre d'impulsion puisque c'est une generation d'impulsion en continue. Vous devez donc modifier cet exemple afin que le compteur 0 ne genere pas en continue notamment en prenant comme exemple le VI finite pulse train qui utilise un compteur comme gating du compteur qui genere.
France.support

Gated event counting for a finite time

I am using a PCI 6110 card for gated photon counting. The digital signal is coming from a single photon counting module, which generates a single TTL pulse upon receiving a photon. It also generates ~100 dark count /sec. To get rid of the dark counts, I use gate pulses with very small duty cycle. In this way, the dark counts are suppressed. I want to operate for a fixed time interal with a resolution of ~1ms. My gate pulses are at 800kHz. Their duration is on the order of 10ns. Is there a way that I can perform gated counting for only 10000 gate pulses? Thanks.

Hi UMeng,
Your question stirred up an interesting discussion at the office. You can't do gated, buffered counting as the gate input is used to trigger the latch to the buffer. We came up with a couple of ideas here, but neither are perfect. It is important to also consider that you are running right at the specifed minimum pulse durations for the gate and source pulse durations for the 6110, which is 10 ns.
NI PCI-6110/6111 Specifications
http://digital.ni.com/manuals.nsf/websearch/A9694D34EF10469386256E3000539747
With that in mind, you could use an external high speed AND gate to generate a signal for a simple event counter to read using the laser gate and the photon detector output as input to the AND gate.
Otherwise, you could try doing gated event counting on the signal and simple event counting on the gate as long as the gate frequency is consistent. Then you could use the frequency of the gate and number of counts of the gate to get the total acquisition time. This will require that you start and stop both counter tasks at as close to the same time as possible. The start could be triggered with an Arm Trigger. Getting the values from the counters would always require 2 software calls, but the longer the acquisition, the less important this error would become.
Let me know if either of these sound appealing.
Regards,
John Bongaarts
AE Specialist - Test Products

Gated-event counting using analog triggers?

I'd like to software trigger gated-event counting with analog signals. eg. Use a comparison to check analog input levels to a 6024E card, once a trigger level is reached send a digital out from the 6024E to a 6601 gate to commence and terminate a counter of the 6601 card.
I have found that the counter on the 6024E card is not stable enough for this application, but the NI-TIO cards work reliably.
Any tips greatly appreciated,
Alan

Alan;
In case you want to trigger a finite pulse train generation of an analog hardware trigger, you can still accomplish that with an e-series board only.
You will need to use both general purpose counters available on the DAQ device though. The first counter needs to be configured as retriggerable pulse generation, having its gate being routed to the AI Start Trigger pulse of the Analog Input task. With that done, the counter will generate a pulse at its output at every time the Analog Trigger level is met. You, then, configure the second counter to execute a continuous pulse train and route the first counter output to the second counter gate input. That will make the second counter to generate a pulse train that will be "enabled" by the first counter. The p
ulse train will be generated while the output of the first counter is on its high state level.
Knowing that, you can configure the pulse width of the first counter to be as wide as you need the second counter to generate the pulse train.
Hope this helps.
Filipe A.
Applications Engineer
National Instruments

Gated semiperiod counting DaqMY LV7.0 + NI6602

I am converting an application form traditional DAQ to DaqMX and am having trouble with the new conventions.
The application uses a common gate to count gated events on multiple counters (5 total counters employed). An event causes 5 pulses of 500us 0.5 duty cycle and the counters must share this gate source and count TTL pulses coming from 4 different photon counting PMT. Essentially I am measuring a optical decay curve (10 points of each 500 microseconds)when each event occurs. This was easily accomplished using traditional DAQ but I cant get it to work under DaqMX (version 7.2). My solution for this scheme under traditional DAQ was to set up 5 tasks, Task 1-4 used counters 0-3 on the 6602 set for semiperiod buffered counting from the source terminal of each counter and the gate was configured to share a common PFI line counter 5 also shared the common gate but used the internal 80MHz clock as a source (This was so I could have a time stamp of each event since the freqency of everns is not a constant. When setting up a semiperiod under DaqMX I can not get the source to change from the internal clock to the PFI corresponding to a counters "source" pin. Any help would be greatly appreciated.
-Paul
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA

Thanks for the help, I was able to get my application to work perfectly, I created a semi-period counting channel then set the timing to implicit continious timing and modified the following channel properities:
1. CI.Dup.CountPrevention = True (I need to allow for zero counts to be valid)
2. CI.SemiPeriod.Term = gate pfi (this allows me to gate multiple channels on a single pfi line)
3. CI.CtrTimeBaseSrc = Source (Pfi line wiered to my PMT ttl line, this is what I need to count)
4. CI.CtrTimebaseRate = 200000 (Maximum expected rate of TTL source pulses, is actually usually much slower ~1-1000kHz)
5. CI.CtrTimeBaseActiveEdge = rising (probably not needed)
6. CI.DataXferMech to DMA (since the 6602only has 3 DMA channels and I configured 4 channels in this mannor, I had to set the last channel to Interrupt, but the application has no trouble keeping pace with the data.
After configuring the channel I start each channel then read them in a loop, now everything is working great, thanks for pointing me in the reight dirrection
-Paul
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA

Gated event counting on 6602

I am trying to use gated event counting or single pulse width measurement techniques to count TTL pulses on two counters during an external gate pulse. The problem is that if zero TTL pulses (a possible condition) go to both counters during the gate, the "armed" attribute does not seem to change from "yes" to "no", allowing the vi to kick out of a while loop and read the value that the counter stored.
Is there a way of setting up the counters so that
1) both counters only collect counts during an external gate
2) zero counts are allowed
3) the counters change state from "armed" to "not armed" at the end of the gate pulse regardless of whether there were TTL pulses on the source channel during the gate?
Thanks,
-Martin

Based on your description of the application, I assume that you are using traditional DAQ. If you have an application where you sometimes expect to have zero source pulses between gates, you should enable synchronous counting (ND_COUNTING_SYNCHRONOUS) (referred to as "duplicate count prevention" in DAQmx). Many of the examples in traditional daq have this as an option that can be enabled on the front panel.
I hope this helps!
gus....

How can I Synchronize two counters in CVI using NI-DAQmx

Hi, I am new to NI-DAQmx, and I would like to program counting of random digital pulses using two counters in LabWindowsCVI and a PCI6229 multifunction card. I have the evaluation copy for CVI 7.1
I would like to set counter0, to count pulses from the 10MHz clock, to generate a single pulse (duration in the few ms timescale), that will gate counter1 in the same card.
When I try to route the output from counter0 to the gate of counter1 I get an error code
(-89137, "The specified route can not be satisfied because it requires resources that are currently in use by another route").
How can one do the equivalent of the "Select_Signal()" in the traditional NI-DAQ?"
I have also a hard time seting the counter0 to actually count a number of clock cycles from the 10 MHz clock.
What is the NI-DAQmx equivalent of the function "GPCTR_Change_Parameter()" to program a counter to count a predefined number of clock cycles?
Any suggestions are welcome.
Fundadero

Hi Fundadero-
It sounds like you're programming for an M Series card with counter operations and need a bit of help with DAQmx functions.
In order to count edges of the 10MHz reference clock you will need to use a format similar to that found in the CVI shipping example "CntDigEv.prj." This is found in the NI Example Finder (Help>>Find Examples) under Hardware Input and Output>>DAQmx>>Counter Measurements>>Count Digital Events. In order to measure pulses from a source rather than the default input terminal (ctrXsource where X is the counter number), you will need to use the function DAQmxSetCICountEdgesTerm(taskhandle char[] counter, char source terminal) as follows:
DAQmxErrChk (DAQmxCreateTask("",&taskHandle));
DAQmxErrChk (DAQmxCreateCICountEdgesChan(taskHandle,chan,"",edge,initialCount,countDirection));
DAQmxErrChk (DAQmxSetCICountEdgesTerm(taskHandle, "/Dev2/Ctr0", "/Dev2/10MHzRefClock"));
What type of operation are you trying to perform on counter 1? The strategy for routing signals will change based on this. If you're trying to perform gated counting you can specify the the task similarly as above and use the terminal "/DevN/Ctr0InternalOutput" as before. If you are trying to perform frequency measurement you will need to use the DAQmxGetCIFreqTerm function.
Other channel properties are listed conveniently in the NI-DAQmx C Reference Help found at Start>>Programs>>National Instruments>>NI-DAQ on your start menu. A search for "channel properties list" returns this list.
Please let us know if you have any additional questions.
Thanks-
Tom W
National Instruments

How do you use the counters on board

I am involved in the development of a LabVIEW VI for the acquisition and processing of signals generated by a chip under test; my application provides two signals having the waveforms sketched in the attached figure.
With reference to this figure, I should generate a digital pulse just after a pulse on signal 1, also in case of no pulses on signal 2.
I am using the board PCI 6110 with LabVIEW 6i: I tryed to use the counters implemented on the board to generate my signal. My idea is to count the pulses of signal 1 with a counter and, if it is possible, to reset the counter on a rising edge of the signal 2. By so doing, when the counter assumes the value “2”, it must generate an impulse. Unfortunately I have not su
cceeded to implement this procedure.
Please, could you suggest me how to implement this solution, or, if this is not possible, any other procedure to accomplish the required task?
Thank you very much for your attention.
Attachments:
figure.jpg ‏17 KB

Hello Gian,
I've tried to think of a method to implement this for a while, but the one fundamental obstacle I keep coming across is that it seems the system must have a deterministic output. (It has to identify the gaps and generate the pulse while on the fly.) It is easy to acquire the two signals and even determining when the gaps occur. The problem is getting your software to recognize this and generate the output fast enough. You could possibly do this with a LabVIEW RT system.
On the other hand, I have thought of a way you could do this with a 660x counter/timer board using quadrature encoder position measurement mode. The problem with the 6110 is that it's counter/timers do not support this mode. With the 660x board in encoder position measurement m
ode, you can wire signal 1 to the source (which increments the counter) and signal 2 to the z-index (which resets the counter to a specified value). You would have this specified value set to be 2 less than the terminal count. If you recieved two signal 1 pulses without any signal 2 pulses, the counter would reach terminal count which triggers a short pulse to be generated on the output and this could be your output signal.
If you do decide to go this route, our technical support can assist you further with this after you have the hardware.
I hope this helps.
Russell
Applications Engineer
National Instruments
http://www.ni.com/support

How do I use AI triggers and counters in DAQ6020-E using LabVIEW 6.0

Hi:
I am new to LabVIEW and sorry for newbie questions. My questions are:
1. I want to use the 2 counters in DAQ6020-E to generate 2 continuous pulse trains(C1 and C2) at different frequencies(C1 @ 1k Hz and C2 @ 2k Hz)and I want to synchronize these 2(for example,they both start with positive edges), how can I accomplish that? should I use a software trigger or a hardware pulse trigger?
2. Followed from 1),there will also be 4 analog inputs(a0,a1,a2,a3) in the same VI. I want them to be triggered by two non-overlapping clock sigals phiA and phiB. phiA and phiB are created by C1 and C2, they both will have 25% duty cycle(with 1k Hz frequency) and are out of phase by 180 degree(thus they wont be bo
th high at the same time).I want a0 triggered by the postive edge of phiA, wait for 0.1 ms, take 1 sample,stop and wait for the next postive edge of phiA. Similarly, a1 will be triggered by negative edge of phiA(wait .1 ms and then sample), a2 by positive edge of phiB, and a3 by negative edge of phiB.
I want to know what pins in the 68-pin connectors corresponding to counter0 and counter1 output, and where should I hook up the triggering phiA and phiB to. Should I initialize them first in Measurement & Automation Explorer?
Thanks so much.
Alan

Hello Alan,
Thank you for contacting National Instruments.
Here are some answers to your questions:
1. You will want to use a harware pulse trigger. This pulse will be connected to the gate of both counters. When a rising edge is detected, both pulse trains will be output on the output pins of the counters. See example attached below.
2. It will not be possible for you to accomplish what you are asking with a DAQPad-6020E. E Series devices only have one analog-to-digital converter (ADC). This means that all 16 channels are multiplexed to a single ADC. This means that it will not be possible to sample(trigger) a0, a1, a2, and a3 simultaneously nor independently. Also, it is not possible to implement the 0.1ms delay from when the edg
e of the sample clock is detected. Here what you can accomplish:
1. You can use an external clock to sample(trigger)a single channel.
2. You can select if you would like the sample your signal on the rising or falling edge of your external clock(phiX).
3. You can use the output of one of the counters as your external sample clock.
I have attached two examples below. One of them generates a pulse train from counter 0. The other acquires analog data from channel 0 by using an external clock.
Here is a link to the DAQPad-6020E User Manual. The output pins for the counter can be found on pages 4-2 and 4-3: http://digital.ni.com/manuals.nsf/websearch/9B5442F668EB7C6B8625669F00743D24?OpenDocument&node=132100_US
Regards,
Bill B.
Applications Engineer
National Instruments
Attachments:
Generate_Pulse_Train_(DAQ-STC).vi ‏103 KB
Cont_Acq&Graph_ExtScanClk.vi ‏108 KB

160 counters in FPGA. Use arrays or 160 loops?

I need to program a 7811R FPGA module to give me 160, 16 bit counters. Originally I made 4 loops (one for each connector) and put the counts from each loop in a 40 element array - mostly to make it easier to program. I'm wondering if that's a bad idea. Would it be better to use an individual loop for each counter? Or maybe use one array per 8 bit port (20, eight element arrays)? I don't have my board yet so I haven't been able to test it.
George

Hello George!
I am terribly sorry I misread your previous question. You want to check for pulses on 160 lines and then keep track of the number of pulses in a 160 element array. I believe this is the only efficent way todo this but I am concerned whether their will be enough real estate on the FPGA to handle this 160 element array. Additionally, its going to take some time to read and process 160 lines at the same time. Therefore you may want to break this up into 20 loops of 8 lines so that you are not waiting for one loop todo all the processing. This would also give you 8 arrays of 20 elements. Sorry it took me so long to get on the same page with this issue. I hope this helps and please continue to write if you have more questions.
Allan S.
National Instruments

Counters gating

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