Crio 9401

Dear,
I have some problems when I use the Crio module 9201, as a digital input!! I don’t know the reason why me program only reads the input in the first scan of the FPGA.
I use an indicator in the front panel, for knowing the behavior of the input but, its indicator it never changes during the running operation. If during the download I have a High TTL level in the physical input, then the indicator becomes green, but if during the download I have Low TTL level, then the indicator becomes red. Then after download operating when the FPGA is running the indicator never changes, as the input was high or low the indicator always maintain the initial value.
I don’t know what happened!!! Everybody know something related to this problem.
Best regards,
Lluís Olivet Cos

Hi,
First of all, apologies me for my reply delay.
Although, I solved the problem 2 minutes after that I post the message .
The problems was that I need to run the FPGA VI first and then run the RT-Module VI. I thought that if I run only the RT-Module VI, the FPGA starting to run too, but it not.
JMota Thanks a lot for your message.
Lluís Olivet Cos

Similar Messages

Fpga/cRIO 9401

Hi there:
I have a problem to use cRIO 9401 as an input for RS232. The very same code works perfectly fine in cRIO 9411, but in 9401 it shifting bits. Is there any configuration should be performed or anything else...?
I will greatly appreciate any help.
Oleg Finodeyev

Hey Vishal,
In order to set a loop time, you should make use of the "loop timer" VI, in the first frame of a sequence structure, and then the rest of the code to execute in the second frame.
For more information on FPGA programming, I recommend that you consult our online LabVIEW 8 FPGA training materials, available here.
Also, ordinarily the 40 Mhz clock is suitable, but it is also possible to create a derived clock. For more information on that, please consult the LabVIEW FPGA Module Help file, or this page.
Best regards,
Message Edited by SamboNI on 06-13-2007 06:14 PM
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Hardware timed Dataacquisition with cRIO

hi,
i am trying to develop a code for dataacquisition using cRIO. my application specifications are:
Digital Input: 1 (trigger for acquisition, i have a cRIO-9401 DIO module
Analog Inputs-2 (i have cRIO-9215 and also cRIO-9221 AI modules for this)
i need to develop a code in which the acquisition is triggered by a pulse signal of Period=20 ms and On-time=1 ms on a falling edge
the two analog inputs are: a current waveform which is on when ever there is a trigger and shuts-off on the falling edge
and the second AI is a voltage signal from an EMI sensor, the two analog inputs should be synchronized
and the code should acquire 20 ms of data after the trigger and check for the trigger again, and if there is a trigger, it should start acquiring
i developed a code for this, but i am having problems with the code......
1) the code seemed to work fine for some time when i tried to test it with two sinusoidal inputs and a pulse as the trigger but when i ran it again, the amplitude of the Analog input was reduced
2) how can i save the data on the Real-time controller? can i do it by using the storage VI's in labview? which i used for storing data on my host computer. and one more thing.....
i saved the data in .tdm format and tried to convert it into .xls using Diadem, but it gave me a warning saying some information can be lost.
Message Edited by jithendra on 08-11-2005 06:38 PM
Message Edited by jithendra on 08-11-2005 06:41 PM
Attachments:
test.zip ‏263 KB

Hello,
By running the VI for a second time, you mean, stop the whole Host VI and the re run it? Or just trigger it for the second time? When you say that it reduced, you mean in Amplitude or the number of samples? I ask this because you have "Data read" that once you write a True to it, it will always be true. You never set it back to False, so the FPGA keeps running all the time, overwriting the "AI Data",
Ricardo S.
National Instruments

Hardware timed Dataacquisition with cRIO

hi,
i am trying to develop a code for dataacquisition using cRIO. my application specifications are:
Digital Input: 1 (trigger for acquisition, i have a cRIO-9401 DIO module
Analog Inputs-2 (i have cRIO-9215 and also cRIO-9221 AI modules for this)
i need to develop a code in which the acquisition is triggered by a pulse signal of Period=20 ms and On-time=1 ms on a falling edge
the two analog inputs are: a current waveform which is on when ever there is a trigger and shuts-off on the falling edge

Hello,
By running the VI for a second time, you mean, stop the whole Host VI and the re run it? Or just trigger it for the second time? When you say that it reduced, you mean in Amplitude or the number of samples? I ask this because you have "Data read" that once you write a True to it, it will always be true. You never set it back to False, so the FPGA keeps running all the time, overwriting the "AI Data",
Ricardo S.
National Instruments

Le noeud de méthode "Set Output Enable"

Bonjour,
J'ai un NI cRIO 9074 avec un module NI TTL High-Speed Digital input/output 9401et je veux savoir si c'est possible d'utiliser un noeud de méthode "Set Output Enable" et comment le configurer car j'arrive pas a trouver la configuracion pour cette option et j'ai le besoin pour finir mon projet.
Merci
hello,
I have a NI cRIO 9074 with NI High-Speed Digital TTL input / output unit 9401et I want to know if it is possible to use a method node "Set Output Enable" and how to configure it because I can not have find configuracion for this option and I need to finish my project.
Thank you

Bonjour ,,
Cette question a déja été posée sur notre forum,
http://forums.ni.com/t5/LabVIEW/How-do-you-configure-a-cRIO-9401-for-output/td-p/365842
Je vous souhaite une bonne journée,
Cordialement,
Sabri JATLAOUI - Certified LabVIEW Developer

Varying ON time pulse train generation using NI cRIO-9073 and NI 9401 module

Hi,
I am a beginner to the Labview environment. Am using NI cRIO-9073 and NI 9401 module; and NI Labview 2013. I want to generate 64 pulses, wherein the ON time of the pulses are varying as shown below. The Pulses need to have a constant period of about 34µs. The pulses should have a constant amplitude anywhere from 5 to 10V. I am trying to do the same in FPGA interface mode but failing to do so. Please advise me..... Please also suggest pdf and video resources to learn Labview programming.
Pulse ON Time
18 µs
19 µs
20 µs
21 µs
22 µs
23 µs
24 µs
25 µs
26 µs
27 µs
28 µs
29 µs
30 µs
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32 µs
31 µs
30 µs
29 µs
28 µs
27 µs
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25 µs
24 µs
23 µs
22 µs
21 µs
20 µs
19 µs
18 µs
17 µs
16 µs
15 µs
14 µs
13 µs
12 µs
11 µs
10 µs
09 µs
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07 µs
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05 µs
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02 µs
02 µs
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05 µs
06 µs
07 µs
08 µs
09 µs
10 µs
11 µs
12 µs
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14 µs
15 µs
16 µs
17 µs

t81,
It is possible to make frequency measurements with either the 9422 or the 9425 but each will have its own limitations in the range of frequency it will be able to accurately measure.
A few things to know:
1. What are the frequency ranges for each sensor (tach and MFM)? More than just knowing Hz/kHz will be helpful.
2. To what accuracy do you need to measure these signals?
The 9422 supports a specialty digital configuration counter input that can be configured for frequency measurement (see link)
http://zone.ni.com/reference/en-XX/help/372603F-01/riohelprt/crio-9422_rt/
The specialty mode is only available when using Scan Interface mode, not with FPGA.
But the max clock rate in the specifications for the 9422 is 4kHz so this may not be sufficient for the tachometer. I believe this is the max rate at which the module will update its state no matter how fast the underlying software (RT controller) is running.
The 9425 has a higher clock rate (~140kHz) but doesn't support the specialty digital mode mentioned above. It is also a software timed only device but this shouldn't be a problem if you use FPGA.
Dan

NI 9401 with cRIO 9073

DearEngineers,
I am using NI 9401 DIO card with cRIO 9073.
I should use 1 channel and generate the frame of 96 bits. The bits will be user configurable. How doi do it. If i get answer to this i shall be able replicat the same with other 3 channels. So my Agenda is to have the frame format generated using 4 independent channels.. Please help me out with the solution and the help shall be greately appreciated
Baud rate of the signal shall be 9.6kbps.
Thanks
Bhargav

Dear All,
Can any body help me with how do i find the CRC for 8 byte Data. Along with Manchester Coding for 8 byte Data

Why do I keep getting error -65581 when trying to use a cRIO 9024 and c series modules

I am simply trying to send out a digital high on DIO0 of a 9401 c series module and I get the following error every time.
Error -65581 occurred at Shared Variable in Send True Value Out.vi
Possible reason(s):
CompactRIO: (Hex 0xFFFEFFD3) The FPGA personality currently running on the CompactRIO chassis does not support the RIO Scan Interface in this slot.
This error or warning occurred while writing the following Shared Variable:
\\NRL-CMG-cRIO\NI 9401-1\DIO0
\\170.126.209.52\NI 9401-1\DIO0
Any help would be greatly appreciated.
Nate
Solved!
Go to Solution.

NMAYO,
In your project view can you right click on the chassis in the cRIO and make sure that it is set for Scan Mode and not FPGA mode? Also, In the measurement and automation explorer you can check the cRIO and verify that it has Scan Engine Support installed on it. The tutorial below shows how to reformat a cRIO and install software on it, the later steps on software will allow you to check your cRIO.
Reformatting a CompactRIO Real-Time Embedded Controller
Ben Sisney
FlexRIO V&V Engineer
National Instruments

No visa resource found - cRIO

Hello,
I have a cRIO chassis with 3 NI-9862, 1 NI-9205 and 4 NI-9401. But in MAX, there is a warning saying that 'No VISA resources found'. And the CAN, analog and digitla IO cards are missing.
Does anyone know how to resolve this issue?
Thanks.

Hi nyc,
I did reboot the computer after the installation of 488.2 on the host. And the target booted as well automatically after the installation.
Right now, the good news is that the 3 CAN cards are available. But the analog and digital cards are still missing.
Thanks a lot for your help.
Jian

Compiler error, unexpected conversion in my cRIO program

Hello,
When I open, or try to run a vi I get this message about 8-9 times,
Compiler error. Report this problem to National Instruments Tech Support.
Unexpected conversion. src type=112, dst type=7
This program is meant to be used on a cRIO system in Real time.
I am using Windows 7, Labview 2011.
This is a rather complex vi, and not yet finished, but here it is along with an image of the error message.
I think that the destination type is an unsigned long integer, while I am not sure about the source type. I have tried to find the instances that tries to convert a data type to an unsigned long integer. I may have missed a few, or I may be chasing my tail.
Thank you!
Attachments:
Control Front end.vi ‏519 KB
error_20120114.PNG ‏27 KB

Hello Joe,
I get this message right when I open the vi, or whenever I compile this vi. This vi calls a vi on the FPGA which is onboard the chassis.
The hardware that I am using is:
cRIO-9022 (cRIO)
cRIO-9114 (chassis)
NI 9401 (DIO module)
NI 9205 (Analog Module)
The arrow is broken, but only says that the vi failed to compile. This does not point me to anything.
I have gone through each part of the code to try to find the culprit. It seems that in my FPGA call (read/write control) I select which channel on the modules to either ouput or read with my FPGA. If I take this portion out of my code, then the error stops and I can run my vi. I've since modified the FPGA code to handle this differently, but I feel like this is not the correct solution, just ignoring the problem.
So my question is: Is it possible to select a FPGA I/O channel from the cRIO vi? If I try, I get an error indicating that I have incompatible type wired up. Although I have copy and pasted directly the channels from my FPGA vi to my vi on the cRIO.
Thank you!
Samuel

CRIO rt timed loop w/ external clock trigger???

I have a feedback control system using a cRIO-9022 and an NI-9401 digital I/O module (among others). I want to use a timed-loop in my RT code to have the execution priority I require. I need to run the timed-loop from an external clock on the NI-9401 input pin. How can this be done?
Thanks,

Hi WhyNot,
Can you elaborate on whether you are using your cRIO's Scan Interface or FPGA Interface to communicate with your 9401? This will make a large difference on your ability to time Real-Time execution with edges coming into your 9401. If you are using the FPGA interface, you may either consider implementing timed loops directly on your FPGA (if the code is not too large), or using a FIFO read from your 9401 on your controller to programmatically gate the execution of your loops. The latter option will not technically be hardware timed but may achieve jitter rates on an order of magnitude of 10s-100s of microseconds depending on your code complexity. If you are using Scan Mode, you may still programmatically gate loop execution based on 9401 inputs but latency will be significant (several milliseconds).
Regards,
Chris E.
Applications Engineer
National Instruments
http://www.ni.com/support

CRIO motor control using AMC Drive

Hi
I am trying to setup a simple DC motor control system with cRIO-9081, NI 9401 and AMC PWM servo drive 12A8. Can someone please tell me if this AMC drive is compatible with my other NI products? Do I need anything else to setup a simple closed loop speed control for a small DC motor? Any advice or example is very much appreciated.
Thanks

Hi SunnyX,
It seems like your servo drive is expecting an input of +/-10V analog. Are you able to confirm this in the device manual? If that is correct, you will not be able to generate the necessary signal with the 9401. You will need another module that you can program to output this signal such as the 9263.
You could also consider using the modules designed specifically for motion control and the SoftMotion Module to simplify the motion control programming. Please let me know if you have any additional questions or comments! Thanks.
Regards,
Kira T

Utilisation du crio-9072 avec signalexpress

Est-ce possible d'utiliser le crio-9072 avec signalexpress.
En fait, j'ai passer la journé à essayer d'accéder au valeurs numérique du module ni-9401 installé dans le chassi 9072. Je suis en mesure de voir le crio dans max mais je suis incapable de voir les module c série. Quel est l'erreur fondamental que je fait?.
Est-ce qu'il faut absolument créé une VI et l'installé sur le crio pour pouvoir l'utilisé?
J'ai installé les dernier driver pour le crio, max, signalexpress, et...
Ce matin j'arrivais à voir les variables tel la mémoire et le cpu du crio dans SignalExpress. Après avoir installer les soft associé au crio dans max tel que décrit dans la procédure sur ce site, je suis incapable d'y accéder de nouveau.
J'ai acheter ce chasis dernièrement. Le but est de réaliser des essais de vibration et mise ne service. Donc, je veux pouvoir enregistrer des signaux divers sur mon PC. J'ai crus que cet équippement ferais le boulo. Est-ce que je me suis trompé?

Bonjour Vinythewheel,
De base, SignalExpress n'est pas fait pour appeler un CompactRIO (des "filouteries" sont toujours envisageables). SignalExpress permet en premier lieu de faire une programmation rapide d'E/S tout en assurant l'enregistrement sur disque. Le matériel nativement supporté sous SignalExpress est le matériel basé sur le driver NI DAQmx et certains instruments répondant au spécification de l'IVI.
Les modules de la serie C, tel que le NI-9401 sont des modules de conditionnement de signal adaptés au cRIO et pour la plupart au cDAQ qui lui peut-être appelé par le driver DAQmx.
La différence essentielle entre cDAQ et cRIO est la suivante:
le cDAQ est un périphérique USB ou Ethernet qui communique avec votre ordinateur
le cRIO est un système autonome à part entière
Le cRIO, sous MAX, est vu comme un système déporté. La communcation entre le système d'exploitation Temps Réel du cRIO et les modules se fait via le fond de panier du cRIO basé sur un FPGA. MAX ne voit pas les modules de la serie C. Il voit sous le controleur la cible FPGA. Seul un projet LabVIEW vous permettra de venir détecter les modules enfichés dans votre cRIO. Du coup il vous faut impérativement programmer votre cRIO sous LabVIEW pour en définir le comportement.
En fonction de ce qui est installé sur le cRIO, il va publier sur le réseau des valeurs de monitoring du système tel que la charge CPU et mérmoire, du coup le comportement que vous avez observé n'est pas inattendu.
Il faudra qualifier un peu plus votre besoin pour ne pas vous induire en erreur mais il semble que vous ayez besoin d'un cDAQ plus qu'un cRIO. N'hésitez pas à contacter NI France au 01 57 66 24 24. Si votre achat est récent ils pourront peut-etre faire quelquechose pour vous et en tout cas les conseillers en avant-vente vous aideront à éviter ces désagrément.
Bon dimanche,
Flo
Open Diagram First

Reset compteur 9401

Bonjour, merci de prendre le temps de me lire et de me répondre..
1) Comment effectuer le reset du compteur internet d' un module 9401 sur un cRIO ?
2) Comment exporter son VI sur lle cRIO pour pouvoir effectuer des mesures embaquées, les enregistrées puis les lire.
Merci beaucoup

Bonjour Falkinou,
Pour la première question, la réponse se trouve ici : http://forums.ni.com/t5/Discussions-au-sujet-de-NI/RAZ-compteur-9401/td-p/2177722
Pour la seconde, je vous propose d'aller à l'adresse suivante : <link no longer exists>
N'hésitez pas à poser des questions si jamais quelquechose semble obscure.
Romain P.
National Instruments France
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>> NIDays 2011, le mardi 8 février au CNIT de Paris La Défense

Generate Square pulse Using DO module with cRIO 9022

Hello,
I want to generate square pulses of 400Hz using NI 9401 for cRIO 9022. I want to control the frequency from 1- 400Hz from PC using LAbview.

Hi Mekel,
most CompactRIO applications use three separate processors—a Windows PC, a real-time OS controller, and an FPGA. The CompactRIO controller uses the LabVIEW Real-Time OS instead of Windows. The FPGA does not use an operating system because the code is implemented directly in hardware.
The common tasks for the Windows host VI include the following:
• logging data to the PC
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The RT controller VI tasks typically include the following:
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• logging data on the RT controller part of the CompactRIO system
The FPGA VI tasks include the following:
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• control
Communication between I/O modules and FPGA is digital because signal conditioning and ADC is done in the modules. Communication between the RT controller and FPGA uses the PCI bus in the CompactRIO. Communication between the Windows host VI and the RT controller VI normally occurs over the Ethernet.
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