Hardware timed Dataacquisition with cRIO

hi,
i am trying to develop a code for dataacquisition using cRIO. my application specifications are:
Digital Input: 1 (trigger for acquisition, i have a cRIO-9401 DIO module
Analog Inputs-2 (i have cRIO-9215 and also cRIO-9221 AI modules for this)
i need to develop a code in which the acquisition is triggered by a pulse signal of Period=20 ms and On-time=1 ms on a falling edge
the two analog inputs are: a current waveform which is on when ever there is a trigger and shuts-off on the falling edge
and the second AI is a voltage signal from an EMI sensor, the two analog inputs should be synchronized
and the code should acquire 20 ms of data after the trigger and check for the trigger again, and if there is a trigger, it should start acquiring
i developed a code for this, but i am having problems with the code......
1) the code seemed to work fine for some time when i tried to test it with two sinusoidal inputs and a pulse as the trigger but when i ran it again, the amplitude of the Analog input was reduced
2) how can i save the data on the Real-time controller? can i do it by using the storage VI's in labview? which i used for storing data on my host computer. and one more thing.....
i saved the data in .tdm format and tried to convert it into .xls using Diadem, but it gave me a warning saying some information can be lost.
Message Edited by jithendra on 08-11-2005 06:38 PM
Message Edited by jithendra on 08-11-2005 06:41 PM
Attachments:
test.zip ‏263 KB

Hello,
By running the VI for a second time, you mean, stop the whole Host VI and the re run it? Or just trigger it for the second time? When you say that it reduced, you mean in Amplitude or the number of samples? I ask this because you have "Data read" that once you write a True to it, it will always be true. You never set it back to False, so the FPGA keeps running all the time, overwriting the "AI Data",
Ricardo S.
National Instruments

Similar Messages

Hardware timed Dataacquisition with cRIO

hi,
i am trying to develop a code for dataacquisition using cRIO. my application specifications are:
Digital Input: 1 (trigger for acquisition, i have a cRIO-9401 DIO module
Analog Inputs-2 (i have cRIO-9215 and also cRIO-9221 AI modules for this)
i need to develop a code in which the acquisition is triggered by a pulse signal of Period=20 ms and On-time=1 ms on a falling edge
the two analog inputs are: a current waveform which is on when ever there is a trigger and shuts-off on the falling edge

Hello,
By running the VI for a second time, you mean, stop the whole Host VI and the re run it? Or just trigger it for the second time? When you say that it reduced, you mean in Amplitude or the number of samples? I ask this because you have "Data read" that once you write a True to it, it will always be true. You never set it back to False, so the FPGA keeps running all the time, overwriting the "AI Data",
Ricardo S.
National Instruments

Unable to measure frequency below 20 Hz on a NIDAQ 9178 chassis with NI 9402 even while using a hardware timed delay

Hello,
I am trying to measure frequency using NI 9402 in NI cDAQ9178 chassis. I am setting the clock for my counter channel to be my chassis ai Sample Clock.
I am able to measure frequency above 20 Hz. For frequencies less than 20Hz, I get the following error:
DAQmx Error: Multiple Sample Clock pulses were detected within one period of the input signal. Use a Sample Clock rate that is slower than the input signal. Ifyou are using an external Sample Clock, ensure that clock signal is within the jitter and voltage level specifications and without glitches.Task Name: _unnamedTask<0>
Status Code: -201314
Setting the Rate to 1 also not does resolve the issue.
OTHER DETAILS:
* Running on 64 bit, Win7 platform.
* NIDAQmx Driver Version: 14.5
I had posted regarding this earlier and I was told that this might be because the counter is armed immediately before the first sample is taken. The recommendation was to add a hardware-timed delay using the DAQmxSetStartTrigDelay method to the AI task. I have added this delay but I still receive the same error message. The previous post I had mentioned can be found below:
http://forums.ni.com/t5/Multifunction-DAQ/Cannot-measure-frequency-below-20-Hz-on-a-NIDAQ-9178-chassis/td-p/1537274
I have also attached my current code which has the delay. Is this a bug in the driver? If yes, can we have a CAR# to track this?
Thanks.
Regards,
Varun Hariharan
The MathWorks

Alright so I got everything working correctly in both C and LabVIEW code.
The problems is in fact with the first sample, as John_P1 suggested. You simply need to delay that first sample from being requested. It is simple to do this in software instead of hardware.
If you are using CVI, just add #include <utility.h> to the top of your .c file and then add a delay before your DAQmxErrChk (DAQmxStartTask(AItaskHandle)); line.
Comment out / remove the DAQmxSetStartTrigDelay(AItaskHandle,10); line, as it wasn't doing what we thought it would. (Hardware delay).
I added Delay (.05); to delay long enough for the full period of the input signal at 20 Hz.
Depending on your frequency, this value may need to be adjusted. 100ms wouldn't be a bad idea.
This is expected behavior, and I don't think we need a CAR.
Let me know what you think!
-CB

Need urgent help with HSDIO hardware timing

Hi everyone,
I need urgent help regarding HSDIO hardware timing. I've been working in a project which generating serial ramp using HSDIO pxie device.
I'm using clock rate 40MHz and generating 14 bit of boolean for each step of ramp. And I have to generate simply 256 steps ramp.
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What I'm doing right now is with using index of FOR loop as my input data (converting the index into 14bit boolean), then write into pxie device in every iteration,
which means, my data is getting into output in every 1ms time, right? (I'm using windows)
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How can I prewrite my 256 steps ramp, then write them all at once into pxie device. I'm really stuck here.
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Regards,
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hi, thanks for responding.
with using example of dynamic generation with script, I can manage to generate the ramp with controllable delay (generate the whole waveform, including delay with script command, then write to the card).
But I still have 1 question, I can test the output of the generation using oscilloscope and cant see the start delay (I'm writing delay at the start, before generating the ramp). My signal generated at 0 sec.
How can I check this start delay? is there any good example delivered with Labview to check this generation? Somehow I cant use the "dynamic generation and acquisition" example to see my generation (cant figure out how to capture the generated signal).
regards,
Yan.

Using cDAQ timers to repeat a hardware-timed finite-sample pulse train clock

Hi all,
As part of a complex project, I must implement an acquisition hardware interface for a linear motion sensor using the Synchronous Serial Interface (SSI) output common in industrial motion control. (I have a fair bit of experience in digital electronics, but I'm new to hardware timer-synchronized digital I/O in LabVIEW.)
To do this, I need to create a hardware-timed bursted pulse train TTL clock signal. Each burst consists of 25 high-low transitions with a full-cycle period of 2.67 microseconds (375kHz). The output must then be held high until the next burst, which occur at 1ms intervals.
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Solved!
Go to Solution.
Attachments:
Hardware Timed Pulse Train Clock.jpg ‏102 KB

Hey Ryan,
A picture of the behavior you are seeing would be helpful. The NI 9411 should only be reading 50 bits every 1 ms.
It may not be possible to read 25 bits (do you mean 50 bits? 25 high 25 low) and push it to a queue without encountering an overflow error. If you take a look at the above code the digital input will receive 50 sample clocks every 1 ms. This is equivalent to acquiring 50 points every 1 ms which is an acquisition speed of 50 samples/1 ms=50 kHz. The read loop must keep up with the 50 kHz rate otherwise the buffer will overflow. In the above example I’ve set the read to pull 5000 samples (x) with the assumption that the loop will take less than or equal to .1 seconds (y). This yields a software acquisition speed of 50 kHz (5000 samples/100 ms). If the loop speed is faster than 100ms then the 10 seconds timeout on the DAQmx read will allow for the read to block so the FIFO may be filled.
The options available for question 2 are below. They may be used separately or in conjunction.
Move the DAQmx Read for the NI 9411 to its own independent while loop, set the DAQmx Read to acquire 50 samples, do not graph the data, and pass the data to a Queue for processing in a consumer loop. This will increase the loop speed which may allow you to keep up with the 50 kHz acquisition speed. This may not work because the loop speed will need to be 1 ms or less.
Increase the value of the Samples per Channel control that goes into the DAQmx Timing VI. This will increase the DAQmx Software Buffer size. This buys time until you receive an overflow error because the DAQmx Software Buffer is being filled faster than samples are removed.
Read in 5000 sample chunks (producer loop), push this to the queue, and perform the analysis in 50 bit chunks (consumer loop). The additional queue created should allow for the acquisition loop to keep up.
Regards,
Izzy O.
Product Support Engineer
ni.com/support

HT201257 I just bought an imac in september 2012. And i just find out that my microphone is not working. So i did an apple hardware test and with no problems found? I have sound but no one can hear me, not even the computer. Should i bring it back to

I just bought an imac in september 2012. And i just find out that my microphone is not working. So i did an apple hardware test and with no problems found? I have sound but no one can hear me, not even the computer. Should i bring it back to the store

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PXIe-4141 hardware timed 4- channel sweep

In the attached example of FET/BJT characterisation using hardware timed two channel sweep, for each gate voltage the drain values are sweeped.
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For each drain value, V is applied and I is measured. So if there are 2 Vg values and 3 Vd values, the PXI fetches 6 Vd & Id and 2 Vg, Ig values.
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Hello,
Last time I asked for your code but I think that you need more information about the hardware configuration for your PXI. That is why I found some material in the help file of the PXIe-4141 which is given below.
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•Once the sequence runs Sequence Loop Count times, the operation is complete, and NI-DCPower generates the Sequence Engine Done event, as shown in the following figures.
The following figure illustrates a sequence with the niDCPower Measure When property is set to Automatically After Source Complete or the NIDCPOWER_ATTR_MEASURE_WHEN attribute is set to NIDCPOWER_VAL_AUTOMATICALLY_AFTER_SOURCE_COMPLETE.
The figure could you find in the screenshot.　
You can find a screecshot in the attachment.
Regards,
Hossein
Attachments:
Help PXIe-4141.png ‏250 KB

Starting out with cRIO

Hello,
What's the most inexpensive way to start programming for FPGA cRIO based applications? I'm interested in learning to develop for an FPGA and cRIO but can't afford the cRIO, is there an inexpensive way to simulate for these (I think even the realtime drivers may be expensive)
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Go to Solution.

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Certified LabVIEW Architect, Certified TestStand Developer
NI Days (and A&DF): 2010, 2011, 2013, 2014
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Hardware timed Dataacquisition with cRIO

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