Fpga/cRIO 9401

Hi there:
I have a problem to use cRIO 9401 as an input for RS232. The very same code works perfectly fine in cRIO 9411, but in 9401 it shifting bits. Is there any configuration should be performed or anything else...?
I will greatly appreciate any help.
Oleg Finodeyev

Hey Vishal,
In order to set a loop time, you should make use of the "loop timer" VI, in the first frame of a sequence structure, and then the rest of the code to execute in the second frame.
For more information on FPGA programming, I recommend that you consult our online LabVIEW 8 FPGA training materials, available here.
Also, ordinarily the 40 Mhz clock is suitable, but it is also possible to create a derived clock. For more information on that, please consult the LabVIEW FPGA Module Help file, or this page.
Best regards,
Message Edited by SamboNI on 06-13-2007 06:14 PM
-Sam F, DAQ Marketing Manager
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FPGA crio

Buenos días a todos.
Llevo un tiempo trabajando con Crio ni-9022 y un chasis que incluye FPGA , y me da unos errores cuando compila la FPGA, que me son imposible de detectar ya que nombre variables a nivel de FPGA.
El fallo es el siguiente:
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details: ERROR:HDLCompiler:69 - "\NIFPGA\jobs\eeQj0Kk_r41egX9\NI_Munge_Pot_activa_y_aparente_SubVI_vi_colon_Clone1.vhd" Line 640: <res00000029_wo> is not declared. ERROR:HDLCompiler:192 - "\NIFPGA\jobs\eeQj0Kk_r41egX9\NI_Munge_Pot_activa_y_aparente_SubVI_vi_colon_Clone1.vhd" Line 640: Actual of formal out port iinitouttoreshold cannot be an expression ERROR:HDLCompiler:69 - "\NIFPGA\jobs\eeQj0Kk_r41egX9\NI_Munge_Pot_activa_y_aparente_SubVI_vi_colon_Clone1.vhd" Line 654: <res0000002b_wo> is not declared. ERROR:HDLCompiler:192 - "\NIFPGA\jobs\eeQj0Kk_r41egX9\NI_Munge_Pot_activa_y_aparente_SubVI_vi_colon_Clone1.vhd" Line 654: Actual of formal out port iinitouttoreshold cannot be an expression ERROR:HDLCompiler:854 - "\NIFPGA\jobs\eeQj0Kk_r41egX9\NI_Munge_Pot_activa_y_aparente_SubVI_vi_colon_Clone1.vhd" Line 82: Unit <vhdl_labview> ignored due to previous errors. VHDL file \NIFPGA\jobs\eeQj0Kk_r41egX9\NI_Munge_Pot_activa_y_aparente_SubVI_vi_colon_Clone1.vhd ignored due to errors --> Total memory usage is 208304 kilobytes Number of errors : 5 ( 0 filtered) Number of warnings : 3 ( 0 filtered) Number of infos : 0 ( 0 filtered) Process "Synthesize - XST" failed
Start Time: 17:23:45 End Time: 17:34:17 Total Time: 00:10:31,834
Gracias por adelantado
Saludos
Pablo Matatagui

Have you checked the signal level from the accelerometer with any other measurement devices to verify that the 9233 is measuring incorrectly? Is the voltage/current excitation for the accelerometer correct? I am assuming you are using the binary to nominal VI for converting the binary data to the real voltage. Make sure you are using the correct module type for the conversion.
I am attempting to use the binary to nominal VI on the values I see on your front panel, but things are not adding up. I used the 4th LSB Weight and Offset (656368 and -6548405)and the 4th 9233 unscaled Binary value (-7261) and converted it with the Binary to Nominal VI for the 9233 and got 0.00178252 for a nominal value while your VI appears to display 0.0067847. I'm not sure what you are doing different than me.
The low valued power spectrum makes sense because the analog input values are low. If we fix the analog input issue, the spectrum should take care of itself.
Without seeing your code or setup, these suggestions are obviously hypothetical. Your screenshots show the FPGA code ok, but we have no idea how you are handling data on the host side. In the future I would avoid embedding giant screen shots in your post, attachments are just fine. Embedded screen shots are more effective if they only contain a small snippet of code.
Cheers,
Spex
National Instruments
To the pessimist, the glass is half empty; to the optimist, the glass is half full; to the engineer, the glass is twice as big as it needs to be...

"Chassis Temperature" in Analog Input Module for FPGA (cRIO-9201)

I have just gotten my cRIO with a analog module (9201) and a digital output module (9472).
When I place an Analog Input Module on my block diagram and double click it, I can choose from the following inputs:
Channel 0 through Channel 7
AND
Chassis Temperature
I have tried to find any documentation for this "Chassis Temperature" but so far without success.
If I read this input and feed it straight to an indicator, I get values in the range of 120 to 150.. Now, without more information, this number is rather useless. Does anyone know how to transfer this data to a temperature (either in the Celcius scale or the Fahrenheit scale)?
Thank you!
Project Engineer
LabVIEW 2009
Run LabVIEW on WinXP and Vista system.
Used LabVIEW since May 2005
Certifications: CLD and CPI certified
Currently employed.

I still did not find any documentation for this "feature" but I lucked out and found the following:
in the folder: \labview 7.1\examples\FPGA\CompactRIO\cRIO-910x\
you should have a file called:
cRIO-910x support files.llb
in this there is a convert to temperature vi.
To get the raw data as a temperature, it looks like all you have to do is divide the binary data by 4 and the answer will be in Celcius.
Project Engineer
LabVIEW 2009
Run LabVIEW on WinXP and Vista system.
Used LabVIEW since May 2005
Certifications: CLD and CPI certified
Currently employed.

Is it possible to have a multiple FPGA cRIO system?

I am curios if it's possible to have a single cRIO chassis that can be expanded with additional FPGAs for computations. Meaning, I don't need more I/O but I do have algorithms taking up too much space and need a secondary FPGA to do some parallel processing. Data would be generated in the first FPGA and communicated to the second FPGA where additional processing takes place and then a response/command is sent back to the first FPGA to then be sent out through the I/O.
I saw something "similar" to this in PXI: http://zone.ni.com/reference/en-XX/help/372831C-01/p2pstreamhelp/p2plv_topo_pipelinefpga/
Althought this solution is dependent upon the PXIe bus it has the general feel for what I'd like. However, I need this in cRIO. Is there a solution that I've missed in my browsing of NI.COM?
It would be OK if the solution consumes one of the cRIO chassis slots.
Solved!
Go to Solution.

A cRIO chassis only has 1 FPGA on it. You may be able to get an expansion chassis and pass the data off to it in order to do the processing. For what you are talking about, though, you would likely want to add some DIO so that you can directly communicate with the expansion chassis instead of going through the RT and Scan Engine.
Alternatively, get a cRIO that has a bigger FPGA and/or get with your local NI representative to see if you can get some time with an NI systems engineer who can help you optimize your code to fit on a single FPGA.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
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FPGA CRIO LabView - Why No Signal or Low signal?

I'm programming LabView 8.2/RealTime 8.2 on a CRIO-9002 equipt with a 9102 chassis. I have a some 4-20mA modules, +-10v modules and last but MOST IMPORTANTLY a 9233 +-5v module.
I've programmed the FPGA and realtime and have been able to acquire and scale appropriatly for all modules except the 9233. The 9233 is hooked up to a VibraMetrics 7002 accerlometer. (http://www.vibrametrics.com/downloads/specsheets/Model%207002.pdf)
When run and an acceleration is applied I only see very low voltage on my display. Why is my 9233 is being unresponsive?
Test run at 3.5 Gvms of acceleration: (please excuse the mess)
Once again, the power spectrum should not be showing levels so low.
Thanks for your help in advance,
Craig

Have you checked the signal level from the accelerometer with any other measurement devices to verify that the 9233 is measuring incorrectly? Is the voltage/current excitation for the accelerometer correct? I am assuming you are using the binary to nominal VI for converting the binary data to the real voltage. Make sure you are using the correct module type for the conversion.
I am attempting to use the binary to nominal VI on the values I see on your front panel, but things are not adding up. I used the 4th LSB Weight and Offset (656368 and -6548405)and the 4th 9233 unscaled Binary value (-7261) and converted it with the Binary to Nominal VI for the 9233 and got 0.00178252 for a nominal value while your VI appears to display 0.0067847. I'm not sure what you are doing different than me.
The low valued power spectrum makes sense because the analog input values are low. If we fix the analog input issue, the spectrum should take care of itself.
Without seeing your code or setup, these suggestions are obviously hypothetical. Your screenshots show the FPGA code ok, but we have no idea how you are handling data on the host side. In the future I would avoid embedding giant screen shots in your post, attachments are just fine. Embedded screen shots are more effective if they only contain a small snippet of code.
Cheers,
Spex
National Instruments
To the pessimist, the glass is half empty; to the optimist, the glass is half full; to the engineer, the glass is twice as big as it needs to be...

Using FPGA cRio and 9853 for a J1939 CAN

We are currently trying to interface with a J1939 CAN network using a cRio 9012, 9104 chassis and the 9853 module. We have Labview 8.2. I stumbled accross the examples for Labview 8.6 and newer. Is there any particular solution/road we should be going down?
I have experience using Labview with a cDAQ, but have not much experince with RealTime and FPGA.
I got the thermocouple module to work using FPGA, so the RIO itself and the module do work.
Thanks for any guidance/help you can send my way.

The way I would approach J1939 on the cRIO would depend on what features of J1939 you needed for your app. If you are just reading or writing broadcast messages that fit in a single 8 byte frame it will be just as straight forward as standard CAN. Basically in this case you would be reading frames on the FPGA code, transmit them to the realtime portion where you can convert them to channel data using a CAN database. Writing would be just the opposite direction.
If you are using requests for PGN data, lets say to retrieve DTC codes, or R/W data using advance diagnostic messages (say DM14/15/16 for example) things will get a bit more difficult but not too bad. If you are expecting to tx or rx multi-frame packets and need the transport protocol of J1939, then things can get complex fast.
DMC recently developed a set of J1939 protocol drivers for LabVIEW which are based on the NI-CAN channel API. The drivers were written in LabVIEW just like the NI frame example, but provide functions at a layer above the base CAN channel API layer. This allows the simultaneous capture of data from both J1939 packets which are simple broadcast CAN frames, or more complex transport using BAM, including extended data frames.
I suppose something like this could be written into the realtime of the cRIO, and just pass frame data back and forth using some very basic code on the FPGA.

Fpga crio Vibration template error code 63192

Dear all,
I'm using the crio vibration data logger template and i'm seeing the error code 63192 from the FPGA reference from the DAQ Thread.vi
Please can anyone help with this error message ?
I've re-compiled which hasn't solved this issue and looking up the error code doesn't suggest much else.
Cheers
Attachments:
error message.png ‏31 KB
crio.png ‏63 KB

Hi all,
Customer support pointed me towards a knowledge based articule here
It was suggested the names did not match up from the project and in max. Please see below that my names match up fine. Also as already mentioned i've rebuild the fpga.
Any thoughts from those experienced users ?
Cheers

Fpga crio mysterious activity in program

Hello,
i have the following problem, my crio 9076 (Slot 1 9411, Slot 2 9474) does mysterious things when running the fpga code
every ~108 seconds the hardwar givs an peak at DO 02 from the 9474, it look like the hardware reset the code
maby someone have the same problem with his code
regars
Lex
Attachments:
FPGA_Master.vi ‏51 KB

I haven't looked at your code, but ~108 seconds is about how long it would take for an unsigned 32-bit integer to rollover to 0 if it is incremenented at 40 MHz, which is the default clock speed on most FPGA targets. Is there anything in your VI that would behave strangely if an integer suddenly went from 4294967296 to 0?
Chris M

Fpga cRIO NI 9263

Hello guys, I´m new with the cRIO and FPGA, and I really need your help, I´m just wanna do something with cRIO, like setting onde bit in my module NI 9263, just it.
Just set a bit, independent of the out 0,1,2 no matter what port is. I just wanna set a bit for a little test, and then I wanna read this bit with my NI 9205. thank you for everything. and sorry about my english.
please help me. Leonardo
Note: my cRIO model is NI cRIO-9004

obrigado mauro por vc estar dando atenção para este tópico, bom eu estou fazendo um trabalho, com compactRIO modelo 9004 chassis CRIO 9104, e eu tenho os seguintes modulos incluidos nele. NI 9426 NI 9205 NI 9263 NI 9477 NI 9425 NI 9476 NI 9871 respectivamente acoplados ao meu modulo do CRIO, sendo assim eu estou tentando realizar apenas um teste para setar uma saida digital, como por exemplo da NI 9426 ou NI 9476 que são as que tenho aqui. somente isto simplesmente mandar um bit para a saida, e depois poder receber este bit no meu modulo NI 9425 ou NI 9426 e acumular este bit recebido por esta porta em um indicador.
o problema aqui na FATEC de Catanduva é que nenhum professor sabe fazer isto, e estou a semana inteira vendo os tutoriais e tentando fazer este teste,mas nenhum deles faz uma aplicação simples que é a que eu estou precisando.
se você puder me passar seu e-mail eu te mando os prints que tirei de como estao configurados aqui. agradeço desde já a sua ajuda.

FPGA Crio encoder SSI protocol

Hello everyone
Does anybody work with SSI protocol encoder and Crio FPGA? I wrote a simple program that try to implement this protocol on Crio FPGA, but i obtain chaotic data. I use a rs422-TTL converter to transform encoder signal (Rs422) to TTL signal for Digital high speed NI9401. Anyone could help me? any suggestion?
Thank you
francesco
Solved!
Go to Solution.

Hi Francesco,
take a look to this link.
Bye
ANdrea

Crio 9401

Dear,
I have some problems when I use the Crio module 9201, as a digital input!! I don’t know the reason why me program only reads the input in the first scan of the FPGA.
I use an indicator in the front panel, for knowing the behavior of the input but, its indicator it never changes during the running operation. If during the download I have a High TTL level in the physical input, then the indicator becomes green, but if during the download I have Low TTL level, then the indicator becomes red. Then after download operating when the FPGA is running the indicator never changes, as the input was high or low the indicator always maintain the initial value.
I don’t know what happened!!! Everybody know something related to this problem.
Best regards,
Lluís Olivet Cos

Hi,
First of all, apologies me for my reply delay.
Although, I solved the problem 2 minutes after that I post the message .
The problems was that I need to run the FPGA VI first and then run the RT-Module VI. I thought that if I run only the RT-Module VI, the FPGA starting to run too, but it not.
JMota Thanks a lot for your message.
Lluís Olivet Cos

RS232 with FPGA crio - anyone done this ?

Does anyone have code to receive RS-232 with FPGA? I have downloaded RS-232 example that contains RS-232 transmit code, i just need receive to complete my interface. any FPGA code would be appreciated.

Attached is an updated version of the code on DevZone for LabVIEW FPGA 8 which includes code for reading and writing RS-232 data.
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
or for use in hazardous environments. You assume all risks for use of the Code and use of the Code is subject
to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense
Attachments:
RS232xmpl.zip ‏528 KB

Hardware timed Dataacquisition with cRIO

hi,
i am trying to develop a code for dataacquisition using cRIO. my application specifications are:
Digital Input: 1 (trigger for acquisition, i have a cRIO-9401 DIO module
Analog Inputs-2 (i have cRIO-9215 and also cRIO-9221 AI modules for this)
i need to develop a code in which the acquisition is triggered by a pulse signal of Period=20 ms and On-time=1 ms on a falling edge
the two analog inputs are: a current waveform which is on when ever there is a trigger and shuts-off on the falling edge
and the second AI is a voltage signal from an EMI sensor, the two analog inputs should be synchronized
and the code should acquire 20 ms of data after the trigger and check for the trigger again, and if there is a trigger, it should start acquiring
i developed a code for this, but i am having problems with the code......
1) the code seemed to work fine for some time when i tried to test it with two sinusoidal inputs and a pulse as the trigger but when i ran it again, the amplitude of the Analog input was reduced
2) how can i save the data on the Real-time controller? can i do it by using the storage VI's in labview? which i used for storing data on my host computer. and one more thing.....
i saved the data in .tdm format and tried to convert it into .xls using Diadem, but it gave me a warning saying some information can be lost.
Message Edited by jithendra on 08-11-2005 06:38 PM
Message Edited by jithendra on 08-11-2005 06:41 PM
Attachments:
test.zip ‏263 KB

Hello,
By running the VI for a second time, you mean, stop the whole Host VI and the re run it? Or just trigger it for the second time? When you say that it reduced, you mean in Amplitude or the number of samples? I ask this because you have "Data read" that once you write a True to it, it will always be true. You never set it back to False, so the FPGA keeps running all the time, overwriting the "AI Data",
Ricardo S.
National Instruments

Hardware timed Dataacquisition with cRIO

hi,
i am trying to develop a code for dataacquisition using cRIO. my application specifications are:
Digital Input: 1 (trigger for acquisition, i have a cRIO-9401 DIO module
Analog Inputs-2 (i have cRIO-9215 and also cRIO-9221 AI modules for this)
i need to develop a code in which the acquisition is triggered by a pulse signal of Period=20 ms and On-time=1 ms on a falling edge
the two analog inputs are: a current waveform which is on when ever there is a trigger and shuts-off on the falling edge

Hello,
By running the VI for a second time, you mean, stop the whole Host VI and the re run it? Or just trigger it for the second time? When you say that it reduced, you mean in Amplitude or the number of samples? I ask this because you have "Data read" that once you write a True to it, it will always be true. You never set it back to False, so the FPGA keeps running all the time, overwriting the "AI Data",
Ricardo S.
National Instruments

How do you create the FPGA I/O Start Node shown in the NI 9233 Getting Started FPGA VI

The fourth frame of the sequence structure in the NI 9233 Getting Started (FPGA) VI (from examples, browse by task, Toolkits>>FPGA>>cRIO>>AI>>Modules>>9233) shows an FPGA I/O node with a Start Terminal. Can someone tell me how to generate the Start Terminal in an FPGA I/O Node?

The Start and Stop terminals of the 9233 module are handled the same as digital lines from DI and DO modules. To access them in the diagram you first need to add them as digital I/O channels in the project.
Once you have added the 9233 module to the project, select to add I/O channels to your project. Instead of adding analog channels, go to the Digital Line Output section (see attached image) and select the Start and Stop signals from the 9233.
Back in your diagram you can then add a FPGA I/O node and select these signals.
Message Edited by Christian L on 12-11-2006 04:41 PM
Christian Loew, CLA
Principal Systems Engineer, National Instruments
Please tip your answer providers with kudos.
Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
or for use in hazardous environments. You assume all risks for use of the Code and use of the Code is subject
to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense
Attachments:
9233iochannelconfig.JPG ‏38 KB

Fpga/cRIO 9401

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