Dual-core Ivy Bridge and gcc -march

Hi,
I wanted to give the ck-kernel a try, and, as indicated in the [repo-ck] wiki page I ran
gcc -c -Q -march=native --help=target | grep march
to see what package is best for me. It says
-march= corei7-avx
which is surprising, because, according to wiki, it corresponds to a Sandy Bridge processor. However my processor is an i7-3517U, which is a mobile dual-core Ivy Bridge processor.
vendor_id : GenuineIntel
cpu family : 6
model : 58
model name : Intel(R) Core(TM) i7-3517U CPU @ 1.90GHw
Any idea of what it's going on here?

@graysky Last week i noticed the same thing the OP did (I have a ivy i7 3770 though). However if you take a look at the [enabled] features from gcc -c -Q -march=native --help=target | grep enabled
-m64 [enabled]
-m80387 [enabled]
-m96bit-long-double [enabled]
-maes [enabled]
-malign-stringops [enabled]
-mavx [enabled]
-mcx16 [enabled]
-mf16c [enabled]
-mfancy-math-387 [enabled]
-mfentry [enabled]
-mfp-ret-in-387 [enabled]
-mfsgsbase [enabled]
-mglibc [enabled]
-mhard-float [enabled]
-mieee-fp [enabled]
-mpclmul [enabled]
-mpopcnt [enabled]
-mpush-args [enabled]
-mrdrnd [enabled]
-mred-zone [enabled]
-msahf [enabled]
-msse [enabled]
-msse2 [enabled]
-msse3 [enabled]
-msse4 [enabled]
-msse4.1 [enabled]
-msse4.2 [enabled]
-mssse3 [enabled]
-mstackrealign [enabled]
-mtls-direct-seg-refs [enabled]
All of the features that ivy bridge are supported are there MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C.
I am unsure however if there are any other optimisations which occur differently between corei7-avx and core-avx-i as i am not going to try and understand the full inner workings of gcc.
However i did manage to patch gcc to enable core-avx-i support when asking for -march=native except that i am unsure of and repercussions of doing so https://github.com/crondog/misc-patches

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Architecture / Microarchitecture
Microarchitecture
Ivy Bridge
Processor core
Ivy Bridge
Core stepping
E1 (QCF5, SR0UX)
CPUID
306A9 (QCF5)
Manufacturing process
0.022 micron
1.4 billion transistors
Die size
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Data width
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The number of cores
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The number of threads
8
Floating Point Unit
Integrated
Level 1 cache size ?
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4 x 32 KB data caches
Level 2 cache size ?
4 x 256 KB
Level 3 cache size
6 MB
Physical memory
32 GB
Multiprocessing
Not supported
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MMX instructions
SSE / Streaming SIMD Extensions
SSE2 / Streaming SIMD Extensions 2
SSE3 / Streaming SIMD Extensions 3
SSSE3 / Supplemental Streaming SIMD Extensions 3
SSE4 / SSE4.1 + SSE4.2 / Streaming SIMD Extensions 4
AES / Advanced Encryption Standard instructions
AVX / Advanced Vector Extensions
F16C / 16-bit Floating-Point conversion instructions
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