Error in Compiling onto FPGA

When I try to compile my FPGA code generated from the FPGA wizard I get this error
An error occurred attempting to connect to this compile server.
Details:
LabVIEW: An exception occurred within the external code called by a Call Library Function Node. The exception might have corrupted the LabVIEW memory. Save any work to a new location and restart LabVIEW.
I already tried uninstalling and reinstalling xilinx

Labview 12.0
Xilinx 13_4
I've only attempted to compile code created by the wizard
Attachments:
Error Screenshot.JPG ‏160 KB
ni_support.zip ‏319 KB

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I am a FPGA freshmen and feel really puzzled.
Thank you!!

Thanks Mike,
I checked the directory according to the steps. Both the path and the configure are correct. Let me express the problem more specifically:
1.Start to compile, the client displays�Successfully started compile�
2.Several seconds later, the server displays�Unable to spawn compiler�
3.Then the client displays"Board clock of 40MHz Met:No(0MHz)"
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Hi I get the attached error when I build my LabVIEW project.
I use Xlinx 14.7 to complie the code and the code is developed in LAbVIEW 2013 fp2
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I changed the server to local from Tools\Options\FPGA Module
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Hi experts ,
While deploying the VC model , i m getting this error :
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You have to remove few components from your model to decrease the compiler generated LOC.
Check the following link for detailed solution:
https://websmp130.sap-ag.de/sap(bD1lbiZjPTAwMQ==)/bc/bsp/spn/sapnotes/index2.htm?numm=936390
Taken from SAP Notes:
<i>Solution
Doing the following may help:
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c.Minimize the use of animations in your models, including form
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3.For on-the-spot, temporary workarounds, you can try dragging an empty
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I have a project that was mostly developed in LV 2013 SP1. I recently upgraded to LV 2014 SP1, and I can no longer compile the FPGA VI. At first, I received an error stating that the Xilinx Vivado 2013.4 compilation tool was not installed. I found this tool on your site, downloaded it, and installed it on my computer. When I try to compile now, the compilation advances to a certain point, seems to hang there for a while, and then returns an error stating that toplevel_gen_propImpl.xds cannot be accessed "because it is being used by another process." I have repeated this exact same scenario on both by desktop and my laptop. I've attached a PDF of the error I windows I have received.
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compile_error.pdf ‏114 KB

Hi scg,
I took a look at your file and researched a little bit about your issue, I have not been so lucky with the research since most of the doceuments are related to previous versions of the software, nevertheless it is also what makes me think that the file might be corrupted or some issue related to it so and I have found some tests that you could try:
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2. Turn off the firewall and compile again
3. Restart the compiler Services
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{GLF_LDG_ACC_TRANS.ldg_name} = {@&CH_LDG_GL_ACT_CURR} and
{GLF_LDG_ACC_TRANS.period} = {@&CH_PERIOD_GL_CURR} and
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select doc_ref1
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and doc_ref1 = "GLF_LDG_ACC_TRANS"."DOC_REF1"
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which essentially queries the same table as the main recordset using the same key fields, and returns one row only. However, when I click on the Check button in the Formula Workshop window, I get the error message "Error in compiling SQL Expression : Database Connection Error: '42000:MicrosoftODBC SQL Server DriverSQL ServerIncorrect syntax near the keyword 'select'. Database Vendor Code: 156 '".
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If you know what you're doing, you can add a full select statement into a SQL Expression... And Kurt is correct when he says that it may only return a single row of info. Don is also correct when he says that this not what SQL commands are designed for.
Here's what's happening...
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Hi,
I am trying to build a LabView FPGA VI. During compilation, I always get error stating "LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support". At the time, comiplation process is almost at the end. "Final Timing (place and route)" shows as completed. When Checked the Xilinx log session, at the end it states that " Process "Generate Programming File" completed successfully". However, I do not see any generated bitfile.
When clicked on error details, it shows following:
LabVIEW: An unknown error occurred.
Error -2629 occurred at Error occurred while loading XML string. Invoke Node in niFpgaXml_PrettyPrint.vi->niFpgaWriteBitfileXml_Core.vi->niFpgaCompileWorker_CreateBitfile.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:6460001
Possible reason(s):
LabVIEW: An unknown error occurred.
I tried multiple times but so far no luck to generate bitfile for this VI. What could be wrong here?
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Hi Mark,
Here is the device utilization Summary. My development system is running with Windows-7 (32 bit) with 3GB RAM and Labview 2013.
Device Utilization
Total Slices: 90.0% (11970 out of 13300)
Slice Registers: 40.7% (43258 out of 106400)
Slice LUTs: 71.6% (38103 out of 53200)
DSP48s: 1.4% (3 out of 220)
Block RAMs: 22.1% (31 out of 140)
Timing
40 MHz Onboard Clock
: 40.00 MHz (57.90 MHz maximum)
80MHz (Used by non-diagram components)
: 80.00 MHz (100.19 MHz maximum)
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I'm trying to use the HDL interface node in LV8 FPGA with a PCI-5640R and had the "timing constraint" error when compiling my VI, however, the same VI was successfully compiled on a CRIO-9104, it seems the FPGA on PCI-5640R is not good as the one on CRIO-9104, or I'm not using it right. could you please kindly help me out?
I tested it with the sample code downloaded from NI website
( http://zone.ni.com/devzone/conceptd.nsf/webmain/456722DDDE17986A86256E7B0065EE6F ) which demonstrates using an IP core for a filter. To simplify it, I only keep the HDL Interface Node and the While Loop (see "UsingFilterCore.vi" in attached zip file), and then I created 2 projects including this VI (1 for CRIO-9104, in sub folder "CRIO-9104", the other for PCI-5640R, in sub folder "IFRIO 5640"). When opening the 2 projects separately in LV8.0 and selecting the VI for compile, the one for 9104 passed and the other failed. Here I attach the source code, error message screenshot and the NIReport from MAX, hope you can reduplicate the problem.
Can you help me out？ Thanks very much !
Message Edited by Jerry_L on 03-26-2006 09:28 PM
Message Edited by Jerry_L on 03-26-2006 09:29 PM

Hi Jerry,
I'm just tried to make all these steps by myself (http://zone.ni.com/devzone/cda/tut/p/id/3516). I have generated FIR filter using Xilinx ISE and got *.VHD file which was going to use in HDL Node.
In the Parameters tab of the HDL Interface Node configuration dialog, double-click in the Names column to add parameters. Create parameters as shown below.
Next, switch to the Code tab. Notice that your parameters now appear in the entity section. To complete the next two sections of code, you will need to refer to the filt.vhd file that you generated earlier and interface the filter core to the LabVIEW FPGA execution system.
1. The first problem I met was integrating VHDL code from earlier generated *.VHD file to CODE tab in properties of HDL Node. Content of entity section in *.VHD is not the same that in your attached file. Please check it in attached files. I'm sure this is the main reasen of problem.
Next, switch to the External Files tab. Click the Add File button and select the filt.edn file that you created earlier. This is the EDIF netlist file that you generated earlier.
2. I have no idea where can I get it and when during filter generation using Xilinx ISE it was generated too. How can I get it? I had to use your attached file filt.edn.
3. After that I have made the same schematics like you have in your VI FPGA and try to run. But I've got two error messages:
HDL Interfave node: enable chain not handled. Details: Refer to the documentation for the correct assignments for the enable_out output from your HDL code.
HDL Interfave node: output not handled. Details: Right-click the node, select Configure to open the Configure HDL Interface Node dialog box, and use the Code tab to handle all output parameters.
Actually I need to model FIR filter:
Bandwidth 200-600 Hz
Sampling 8 KHz
Attenuation 80 dB
That's why I tried to follow all these steps by myself to understand how does it work.
Thanks a lot.
Nikita
Attachments:
Filter1.vi ‏16 KB

ERROR:HDLParsers:3370 Compile Error when compiling for NI-5640R

I'm trying to get a FFT Core working inside the NI-5640R FPGA. In my latest debugging step, I have received the following error when compiling:
Compiling vhdl file "C:/NIFPGA82/srvrTmp/LOCALH~1/IFBC3E~1/bushold.vhd" in Library work.
Entity <bushold> compiled.
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Attachments:
FFT (FPGA).vi ‏125 KB
FFTworking (FPGA).vi ‏119 KB

Hi,
The main cause of this error message is the large array size. You configured a 16-bit fixed-size array with 4096 element for a total array size of 65536 (16 * 4096). Array uses a lot of FPGA resource and the general recommendation to limit the use and size of array as much as possible on the FPGA VI. This VI will certainly overmap the FPGA resource because of the large array size.
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Message was edited by:
Martin Wolpers

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