Error in compiling LabVIEW FPGA target

Hi I get the attached error when I build my LabVIEW project.
I use Xlinx 14.7 to complie the code and the code is developed in LAbVIEW 2013 fp2
I also use NI DlexRIO 14, NI-RIO 14.0.1
Thanks
Attachments:
123.jpg ‏99 KB

I changed the server to local from Tools\Options\FPGA Module
But still when I compile it I get this error message. I still can't compile it because it asks for Xilinx 14.4
I have also downloaded 14.4 but I can't insall it because as soon as I try to insatll I get teh attached error
Attachments:
Untitled.jpg ‏125 KB
Untitledwq.jpg ‏45 KB

Similar Messages

LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred

Hi,
I am trying to build a LabView FPGA VI. During compilation, I always get error stating "LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support". At the time, comiplation process is almost at the end. "Final Timing (place and route)" shows as completed. When Checked the Xilinx log session, at the end it states that " Process "Generate Programming File" completed successfully". However, I do not see any generated bitfile.
When clicked on error details, it shows following:
LabVIEW: An unknown error occurred.
Error -2629 occurred at Error occurred while loading XML string. Invoke Node in niFpgaXml_PrettyPrint.vi->niFpgaWriteBitfileXml_Core.vi->niFpgaCompileWorker_CreateBitfile.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:6460001
Possible reason(s):
LabVIEW: An unknown error occurred.
I tried multiple times but so far no luck to generate bitfile for this VI. What could be wrong here?
I am using Labview 2013

Hi Mark,
Here is the device utilization Summary. My development system is running with Windows-7 (32 bit) with 3GB RAM and Labview 2013.
Device Utilization
Total Slices: 90.0% (11970 out of 13300)
Slice Registers: 40.7% (43258 out of 106400)
Slice LUTs: 71.6% (38103 out of 53200)
DSP48s: 1.4% (3 out of 220)
Block RAMs: 22.1% (31 out of 140)
Timing
40 MHz Onboard Clock
: 40.00 MHz (57.90 MHz maximum)
80MHz (Used by non-diagram components)
: 80.00 MHz (100.19 MHz maximum)
--WillsG

Error in Compiling onto FPGA

When I try to compile my FPGA code generated from the FPGA wizard I get this error
An error occurred attempting to connect to this compile server.
Details:
LabVIEW: An exception occurred within the external code called by a Call Library Function Node. The exception might have corrupted the LabVIEW memory. Save any work to a new location and restart LabVIEW.
I already tried uninstalling and reinstalling xilinx

Labview 12.0
Xilinx 13_4
I've only attempted to compile code created by the wizard
Attachments:
Error Screenshot.JPG ‏160 KB
ni_support.zip ‏319 KB

Incremental Compile LabVIEW FPGA

Hello all.
It is time-consuming that we have to compile all LabVIEW FPGA code even if there is tiny little change on FPGA code.
I understand there is sampling probe, Desktop execution node and simulation tools to reduce such time.
Our customer in Japan, would like to use incremental compile function also on LabVIEW.(Please see below)
I agree his opinion.
http://www.youtube.com/watch?v=9v50uCVdW3o
What do you think?
Eisuke Ono
Application Engineer at National Instruments Japan.

I think this is something everyone would like to see, I'm glad someone finally posted an idea for it to get feedback from the community. With the introduction of (better) incremental compilation in the latest 3rd party tools like Xilinx there is certainly some features the LabVIEW FPGA compiler could take advantage of. There is also plenty of optimizations within the LabVIEW FPGA compiler itself that could help.
The problem with incremental compilation of any kind is doing it well enough that the majority of use cases don't suffer performance issues when squeezing application changes into as few changes in the actual hardware. Getting this balance right takes a lot of work and a lot of sample applications to try it against.

There is an error when compile a FPGA example vi

I just run a simple example vi such as Digital.vi and then found an error "Unable to spawn compiler" in the compile server dialog box. It seems that the FPGA vi can not be compiled.
Could you give me some help?
I am a FPGA freshmen and feel really puzzled.
Thank you!!

Thanks Mike,
I checked the directory according to the steps. Both the path and the configure are correct. Let me express the problem more specifically:
1.Start to compile, the client displays�Successfully started compile�
2.Several seconds later, the server displays�Unable to spawn compiler�
3.Then the client displays"Board clock of 40MHz Met:No(0MHz)"
we checked the xflow.log file and it shows CompileServer got an error when calling Xilinx compile tools.
It seems that the error is caused by inexsitence of file toplevel_gen.prj.
Could you give me more help?Thank you
Best reguards,
Yang Xin

LabVIEW FPGA Module Error Code 10 when creating bitfile

I am recieving the following error message when trying to compile a vi:
Internal Error
An internal LabVIEW FPGA Module error occurred at the following stage: Creating Bitfile.
Error Code: 10
Error Text: Create Folder in nirviRecursiveCreateFolder.vi-
>nirviRecursiveOpenFile.vi->nirviWriteBitFileInformation.vi-
>nirviCompileDownload.vi->hardware_template.vi
If this problem persists, please contact National Instruments.
Any help would be appreciated. I am not very familiar with LabView, and am trying to run code generated by a grad student several summers ago. If more information is needed, let me know and I will try to provide it.
Thanks

Arkolbus-
It sounds like the compiler is having some trouble creating a folder that it needs to generate the bitfile. First, check all of the usual things: are you an administrator? do you have worte access to the "FPGA Bitfiles" folder in your project?
If it looks like you should be able to write the file, you can try posting your project (zipped) and let someone on the boards try to compile it (be sure to let us know what the versoin is). If we can compile it without issue you may want to try repairing your FPGA module installation.
Xaq "Bulldozer"

LabVIEW FPGA driver for Xilinx SPARTAN 3E Starter Board

i need drivers for spartan 3E .

If you are at a university that has a site license for the FPGA module, the following might be of interest to you:
Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUP Starter Kit
See also this discussion.
Quote from the license agreement:
...INSTALLATION AND USE OF THE LABVIEW FPGA TARGET MODULE FOR THE XILINX SPARTAN-3E STARTER BOARD (THE “TARGET MODULE”) IS LIMITED TO ACADEMIC INSTITUTIONS THAT HAVE A VALID, CURRENT “ACADEMIC TEACHING LICENSE” FROM NATIONAL INSTRUMENTS FOR THE LABVIEW FPGA MODULE. THIS TARGET MODULE MAY ONLY BE USED FOR INSTRUCTIONAL PURPOSES, SUBJECT TO THE TERMS AND CONDITIONS OF THE NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT THAT ACCOMPANIES THE SOFTWARE...
LabVIEW Champion . Do more with less code and in less time .

Compiling errors under LabVIEW FPGA v1.1

Problems compiling any designs to target PXI-7831R.
Compile Server v1.1 starts but fails after 5 seconds. Details window reports "#SERVER ERROR: Error while Compiling #"
I have checked the configuration and it points to the correct directories. I have removed and reinstalled Labview 7.1 and FPGA module 1.1, but the problem persists.
The design compiles correctly on another machine so it appears to be related to the software installation on this machine.
I have attached the xflow.log report from the srvrTemp directory for this design. It is complaining that it cannot find a VHDL file : nirvi_zerodelayer.vhd
The VHDL file does exist in the clntTmp directory for this design but not in the srvrTmp directory.

Hi, this happened to me regularly. What I use to do is to delete the whole content of "C:\NIFPGA11\clntTmp"
and "C:\NIFPGA11\srvrTmp\localhost". Also, I've noticed that compilation may not fail if I click run instead of build when the target is "FPGA Device (PXI-7831R) <compile only>"... stange!
hope this helps!

Labview FPGA compile stuck at "Place and Routing"

I am using LabVIEW 2010 SP1 32-bit FPGA module. I've built a very large program that was first done back using LabVIEW 8.6, so I have several years experience on LabVIEW FPGA.
When I say it's a large program, I mean that a several times over the last couple years I've tried to add more functionality that has failed to compile do to not enough space on the target or timing restraints. My target has mostly been the PCI/PXI NI-7813R. Due to the nature of our product, a lot has to be done on one FPGA board.
When I do go "over the limit" the compile (after a couple hours) fails and tells me that there's just not enough room on the 7813.
Recently, however, I added some more code, thinking the odds were good that it might push me over the edge. However, the compile never fails. Unfortunately, it never stops either. It gets to the "Placing and routing" portion of the compile and just stays there. When I say stays there, I mean I've run it over night, and when I check it the next morning, the "Elapsed time" is over 10 hours, and still counting up. The device utilization and estimated timing numbers are all under max. And I see no errors in the report so far that I'm used to seeing. Like I said, it just keeps compiling.
I've attached the Xilinx log. It looks much like the log before I added the extra code, except it just stops logging with reporting any useful error.
Anyone have an idea what I could be doing wrong?
Thanks,
Rick
Attachments:
XilinxLog.txt ‏3936 KB

tannerite,
Thanks for your response.
I added code that measures the "on time" of incoming DIO pulses. If the pulses are HIGH for one given amount of time (eg. 60[+/- 5] usecs) it means one thing, if HIGH for a different amount of time (eg. 120[+/- 5] usecs) it means something else. Generally speaking, I just keep a tick count between the rising and falling edge of the pulse, and use the "In Range and Coerce" from the Comparison Functions palette to check where the count lies.
When it compiled successfully, I duplicated the above code for 10 seperate DIOs. Then I realized I needed to monitor 20 DIOs. It was when I added the code for these extra 10 DIOs that I got the "forever" compile. The compile problem occurs everytime I try to compile with the extra 10 DIO code in place. As an experiment, I just added 4 extra DIOs, i.e. code to monitor a total of 14 DIOs. This causes the same compile problem.
And yes, the compile seems to hang in the same place every time it hangs. Like I said, I wouldn't be surprised if I'm just beyond the available resources available. But when I've done this in the past, the compile does finally fail, and I get a useful error message. I've never seen it go "forever".
Thanks ahead of time for any insight you might have.
- Rick

"LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD

The compilation of my labview fpga vi fails with the error message "LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD".
In the 'final timing (place and route)' report, the requested frequencies are all below the maximum frequencies and the compilation error message is only displayed at the very end on the 'summary' page.
I tried to optimize my labview fpga vi with pipelining, but had no success.
Can anybody offer some advice on how to debug fpga code with this error? Is this really a timing error or something else?
Software:
Labview 2011, fpga 2011, xilinx tools 12.4 sp1
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
The Xilinx log of the compilation run is attached.
Also, this issue was already discussed in this thread ~6 months ago, but no satisfying answer was offered so far...
Thanks,
Fabrizio
Attachments:
xilinxlogc.txt ‏2313 KB

Hi Kyle,
the problem is: I have one computer which compiles the VI successfully and a second one which shows that error. Both use the same software setup (LV2011SP1+RT+FPGA from DS2012-01). Both use the same project file - atleast SVN shows no difference.
- You can have one FPGA VI where one computer is compiling successful and a second one complains. (Btw. I have a SRQ running in Germany on this topic.)
- More problems: After successful compiling on first computer and transferring all to second computer (using SVN, including the full project folder with all files like bitfiles, lvproj, and everything) the second computer is unable to start the RT executable due to error "FPGA VI needs to recompile". Solution so far: Call the FPGA-OpenReference with the bitfile instead of the VI (as I used to do until now)...
- More problems: After modifying the FPGA-OpenReference to use the bitfile (on the 2nd computer) and transferring all the files back to the 1st computer (using SVN as before, including the whole project) the 1st computer complains: FPGA-OpenReference is creating a different reference than is used in the VI. So what happens here? On one computer my VI is ok, the reference is typed correctly. Transferring all the files to a different computer the VI isn't ok anymore due to changes of the reference??? You know: all files are the same: lvproj, FPGA bitfile didn't change, cRIO reference didn't change...
All those problems didn't occur on my RT-FPGA projects in LV2010SP1. I'm not pleased...
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

LabVIEW FPGA was unable to contact the Compile Server at "localhost" on port 96.

Hi,
The following error occured when i am trying to compile my design on labview fpga 8.6, and the error reads as follows.
"LabVIEW FPGA was unable to contact the Compile Server at "localhost" on port 96. The server name or port may be incorrect, a firewall may be blocking communications with the server, or the configured timeout may be too low. You may reconfigure Compile Settings by clicking the Configure button or try contacting the Compile Server again by clicking the Retry button. Click the Cancel button to abort."
Can ane one help me in sorting out this error.,
Regards
KalyanSuman KV

This should solve it

Compilation time - LabVIEW FPGA project

I am trying to compile a LabVIEW FPGA project over NI PXIe-1071 chassis.
My problem briefly lies in the compilation time which last hours while only takes approximately 20 minutes on another chassis I am having with exactly the same specifications.
Is there any project settings I should check which may casuing this problem ?
Thanks.

The FPGA boards exactly the same and the VI is exactly the same? All you are changing is the chassis? R Series or FlexRIO? What version of LabVIEW FPGA? How much are the designs "filled up" (like what is the percent utilization of slices)? There are project settings for effort levels of the Xilinx tools depending on what version of LabVIEW you are using.

LabView FPGA ERROR:place:543

Hi folks,
While i'm compiling my FPGA vi,
i have got the device utilization report as 76%...while phase 13.9(during mapping) calculation i'm getting Error:Map:543. placement constraint error..Give me a solution to resolve this issue...
Thanks in Advance....

Hi,
Thanks for your response....
i'm using LV 8.6.1 and RIO version is 3.1.0.
H/Ws are
Controller - cRIO-9014
Chassis - 9114
AI - 9205
AO - 9263
DO - 9476
DI - 9425
Basically i have two FPGA VIs. One VI which just fetches the AO channels' offset & LSB and i could compiled it. Another one i have put the FIFO and other main logics and that could not be compiled..
Here i have attached the compilation summary which i got...
Thanks....
Attachments:
xflow.log ‏2101 KB

I have compiled a program for a target after I added a new vi from NI_AALPro.lvlib. The addition worked fine on my development computer but gave me errors when run on the target.

I have compiled a program for a target after I added a new vi from NI_AALPro.lvlib. The addition worked fine on my development computer but gave me errors when run on the target.
The box displayed:
Missing subVI NI_AALBase.lvlib:1D Linear Evaluation.vi in VI NI_PtbyPt.lvlib:Linear Fit PtbyPt.vi
Missing subVI NI_AALPro.lvlib:MSE.vi in VI NIPtbtPt.lvlib:Linear Fit PtbyPt.vi
What do I need to do to bring the correct library into the transportable code?

Hello,
I was unable to reproduce the behavior that you saw. I was able to deploy my application with the Linear Fit PtByPt without issues.
Could you attach the smallest piece of code that reproduces this behavior so that I can test it as well?
Justin Parker
National Instruments
Product Support Engineer

LabView fpga VHDL code and compiler

Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.

Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer

Error in compiling LabVIEW FPGA target

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