Generating an input signal

I have completed the FPGA Module tutorial and I am attempting to generate an input signal, but i really don't understand exactly what is going on in the tutorial.  I have two FPGA I/O nodes in the FPGA VI that are labeled "ADC 0 PORT A_I" and a corresponding one labeled Q as well.  I'm assuming that these generate a sine wave that the tutorial used as the input signal.  I want the input to be a sine wave with noise, and Mauricio suggested using DDS, but I don't know exactly how to add this to the existing FPGA VI that I created in the tutorial.  Can anyone help me out on this one? 

I'm a bit confused by your post. The FPGA Module tutorial guides you through the creation of a VI that acquires a signal. The I/O nodes labled "ADC 0 Port A I" and "ADC 0 Port A Q" are the I and Q elements of the acquired and downconverted signal. Just to be able to test this code, the HOST VI also configures one of the Analog Output channles in "Single Tone Mode" and therfore generates a sine through it. However, the FPGA is not doing anything to generate the sine tone, it's the DAC which is configured to generate the sine tone.
The I/O nodes that you need to use to generate signals are the "DAC 0 Data" and "DAC 0 TxEnabled". You will also need to use another clock, the "DAC 0 IQ Clk".You might want to read some documentation on the Analog Output and look at the IQ Output example. You can find the documentation on this post: http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=140

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