Hilevel interrupts from a PCI device?

This question has been asked before in this forum but did not really get answered: in Solaris 8 on a SPARC (specifically an UltraSPARC III in a SunBlade 1000), can I force the interrupt from a PCI card to be hilevel? If so, how is it done?
I found the suggestion that this may have once been possible in Solaris in the article at http://soldc.sun.com/developer/support/driver/wps/pci/html/Interrupts.doc.html, but there's no detail on exactly how to do it and the document is dated February 1997. The current driver documentation does not list PCI as one of the bus types that generate hilevel interrupts. But it doesn't say it can't be done either.
Dave

The interrupt level for a PCI device is derived from the Base Class of the device or from the "interrupt-priorities" property which can be found in the driver.conf file. So to change the interrupt level to a hilevel interrupt you should set the "interrupt-priorities" property.
See http://soldc.sun.com/developer/support/driver/wps/pci/html/Interrupts.doc.html

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    Thank you!!

    Thank you for your reply !!
     I am developing pci-7344`s driver under venturecom`s rtx,now I have found the baseadresses[0] and baseadresses[1] . baseaddresses[0] is the base-address of the miniMITE and I can get the vendor ID, device ID by directly reading from baseaddresses[0] +offset,but  baseaddresses[1]  does not like to be the base address of the 7344 registers,because I can not get the correct status information when I read from the csr(baseaddresses[1]+0x04)(all the value read back is 1).According to your advice I add the following codes to the program.
     window_data_value = ( (0xffffff00 & (ULONG)BAR1.LowPart) | (0x00000080) );
            *((PLONG)(vMemAddr[0]+0xc0)) = window_data_value;
      vMemAddr[0] is the virtual address that is mapped from BAR0 into the user`s program ,which gives us access to physical memory locations on the system.
      After adding these codes I still can read the correct information from BAR0,but I still can not read back the correct value from BAR1(all the value read back is 0).
     It says in ddk that the csr(a read-only register) is located at cardlogicaddress+4(8byte offset),so I wonder what  the cardlogicaddress is . What is relationship between baseaddresses[1] and cardlogicaddress?
    Thank you!!!!!

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