Informaciòn sobre la memoria de la FPGA

Estimados,
Tengo una intertrogante. Estoy trabajando un NI cRIO 9004 y quiciera saber todo lo relacionado con la memoria de la FPGA. Por ejemplo saber cuanto estapacio lleva ocupada, como borrar lo que ya tiene o como respaldar esos archivos creados ya que quiero agragr VI's a la fpga pero nose si tengo espacio suficiante o como es el sistema que ocupa la memoria. Si tengo mal el concepto les pido disculpas ya que soy nuevo en esto de la FPGA.
Saludos

Siga el sitio de las especificaciones de la cRIO-9004. Y la FPGA se recomienda. Pero todo lo que se especifica en la hoja de datos.
Cualquier pregunta apenas hablar.
Atentamente.
http://sine.ni.com/nips/cds/view/p/lang/pt/nid/14161
NI LabVIEW FPGA Module
Create your own I/O hardware without VHDL coding or board design
Graphically configure FPGAs on NI reconfigurable I/O (RIO) hardware targets
Define your own control algorithms with loop rates up to 200 MHz
Execute multiple tasks simultaneously and deterministically
Implement custom timing and triggering logic, digital protocols, and DSP algorithms
Incorporate existing HDL code and third-party IP including Xilinx CORE Generator functions
Erick Yamamoto
Application Engineer
National Instruments Brazil
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Similar Messages

How exactly does the memory in Labview Fpga work

I am using a PXI 7853 and I for the past few days I have been playing around with using Memory blocks in the FPGA .
Now I am relatively new to Labview FPGA programming and hence I would be grateful if someone could provide me with clarifications on teh following :
a) Since I am working on the development host computer when I initialize the Memory with the option of using a Memory initialization VI then how does it exactly happen in the backend .What I mean to ask is , when i change values of memory in the development computer and then compile the FPGA VI into the board ,is it that the Memory information is ported into the FPGA .If this is the case then in what form are the details initially saved in the development computer .
b) Is it possible for me to use the initialization VI method to change the valuesi n memory while the FPGA VI is running .If not ,then would it make a difference if I stop the VI and then change the values using initialization method .Would that actually reflect on the FPGA or should I have to re compile the FPGA VI every time I change the memory values in the development computer using the 'Initialization VI method ( that is available as an option when we right click on the memory block in the project explorer window )
I tried testing with simulation for FPGA VI and found that when i try to change the memory values by running the initialization VI . a pop up comes that says that it is not possible as the FPGA VI is still in use .
Any light on this or guidance with links would be highly appreciated
Cheers
sbkr
Solved!
Go to Solution.

sbkr wrote:
a) Since I am working on the development host computer when I initialize the Memory with the option of using a Memory initialization VI then how does it exactly happen in the backend .What I mean to ask is , when i change values of memory in the development computer and then compile the FPGA VI into the board ,is it that the Memory information is ported into the FPGA .If this is the case then in what form are the details initially saved in the development computer .
When you compile the FPGA VI, it will include the values used to initialize the memory.
Are you asking what happens if you run the FPGA VI on your development computer, and your FPGA VI writes to the memory block, will the new values be included when you compile the FPGA VI? No, those values will be lost. The values that are included in the bitfile are the values that you used to initialize the memory block, as defined in the memory properties dialog box. The initial values are saved in the LabVIEW project file along with the memory block definition.
sbkr wrote:
b) Is it possible for me to use the initialization VI method to change the valuesi n memory while the FPGA VI is running .If not ,then would it make a difference if I stop the VI and then change the values using initialization method .Would that actually reflect on the FPGA or should I have to re compile the FPGA VI every time I change the memory values in the development computer using the 'Initialization VI method ( that is available as an option when we right click on the memory block in the project explorer window )
You need to recompile the FPGA in order to use new initialization values, because those values are part of the FPGA bitfile.

Available memory in myRIO FPGA

How can I know the memory address of the RAM in FPGA,to inteface with my devices?
Hope someone could answer my confusion:-(
Thanks a lot!
Allenguo

I see from your signature that you have Norton Anti-virus. Get rid of it.
Norton Antivirus has a very long and illustrious reputation for mangling Mac OS X systems, sometimes to the point where a complete reinstall is necessary. Among other things, it installs kernel extensions which are known to cause kernel panics and system freezes; it contains known and documented bugs which can silently corrupt Adobe Photoshop and Adobe InDesign files, destroy a user's ability to authenticate as an administrator, and (on PPC systems) can cause Classic to stop functioning; and Symantec has on at least two occasions now released flawed .dat file updates which erroneously report certain critical Mac OS X files as "viruses." (Deleting these "viruses" causes damage to the system that in some cases renders it unbootable.)
Also, you need to to update to OS 10.4.11.
And of course clean out your caches!

FPGA memory limitation

Hi...
I have tried to use more than 2 MB memory (using memory blocks) on FPGA. During compilation Xilinx tool chain generated error "AR #21955"....which is explained as memory limitation (in xilinx website). Can't we create memory blocks of more than 2 MB?? (or) all memory blocks size in a vi should not cross 2 MB??. I need to create arbitrary wave forms of milli/micro second precision for some minutes......so i need many no. of points to get required waveform....Is there any way to achive it....when I transfered each point from a RT vi (not on FPGA) it takes more time (to transfer data from RT vi to FPGA vi for every iteration).
Thank you,
Cheers,
Ravinder

The size of the memory blocks you can allocate in the project and use in your FPGA VI is limited by the size of the memory available on your FPGA device. This memory is in the range of 80-192 kB depending on which FPGA device you are using. Please check the data sheet or manual for your device for details.
http://sine.ni.com/manuals/
So unfortunately you will not be able to store the complete waveform on the FPGA device.
Your best option is to stream the waveform from host memory to the FPGA device using DMA and generate the data from the DMA FIFO in the FPGA VI.
Message Edited by Christian L on 08-06-2008 06:24 PM
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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Trigger two FPGA instances at same time

I have some basic FPGA code that transmits data bits over a serial bus (RS485), The code is written so that it waits in the first state of a state machine in a single cycle timed loop. Upon a certain trigger, it starts reading a FIFO containing data and sends the data out on a Tx line. It does this until all bits are send then it goes back to the first state to wait for the next trigger. The trigger is needed because windows has to fill the FIFO first before the FPGA can start sending.
I need two instances of this code running because I have two com busses (one is redundant). So I am using the FPGA code as a subvi and I wrote a main FPGA vi to call two separate instances of the subvi in parallel. A regular windows vi writes to the FIFOs for Tx and reads FIFOs for Rx. No problem so far.
The trick is that I have to start both transmissions within 200nS of each other (yes, nanoseconds). Windows will write to both FIFOs in parallel, but the timing is 4uS apart, too long. I tried setting up a boolean flag in the FPGA subvi, but windows can't write to the subvi control directly. FPGA won't allow it (the Write function is greyed out). I tried using a FIFO for a flag, but the problem is a race condition. One of the instances will read the FIFO first and wipe it out. The other does not get to read it. I need one common trigger point to be used by both subvi instances.
My final solution was to use a memory in the FPGA subvi and a numeric control in the main FPGA vi. Windows write to the numeric control, It can because the control is in the main FPGA vi. Inside the main FPGA, I run a timed loop that looks for the numeric to be other than zero. If so, it writes the value to the memory location used by the FPGA subvi. After some time, the main writes a zero back to the memory to prevent the subvi from starting up again, and it writes a zero to the numeric to reset it. The whole thing repeats, waiting for windows to write to the numeric again for the next transmission.
I had to do it this way because sometimes I want to transmit on both busses, and sometimes just one or the other. Numeric values are used to determine which to transmit on. Now the transmissions start at almost exactly the same time, 1 or 2 nanoseconds apart. But the trigger process seems very far fetched to me. I was wondering if there is a better solution. I'm pretty new to FPGA.
- tbob
Inventor of the WORM Global
Solved!
Go to Solution.

tbob wrote:
Basically I did the same thing using FPGA Memory. From windows I write to a numeric control which resides inside the FPGA Main vi. In the FGPA main, I write to the Memory. Inside the FPGA subvi, I read the memory and decode the value to either use one or the other or both busses. After fooling with this for some time, because the Read Memeory needs to use a shift register (probably due to it taking an entier clock cycle), I got it to work. Both busses trigger at the same time. I guess it really doesn't matter if I use a FIFO or if I use Memory. The main issue is that I have to write from Windows to the FPGA Main, and then from the FPGA Main to the FPGA subvi. Then the timing is exact as far as the subvi is concerned.
There are a couple of advantages to using two FIFOs over your approach. First, you don't need the shift register for the memory location. Second, you don't have to worry about which VI is responsible for clearing the memory location, nor do you run the risk that one of your subVIs will execute twice, or not at all, if the memory isn't cleared at the right time. Perhaps most importantly, you'll save yourself space on the FPGA because you won't need arbitration - the extra code that gets added when two parts of the FPGA try to access the same resource at the same time. In your case, both instances of the subVI access the memory block concurrently, so the FPGA compiler adds extra logic to prevent conflicts. If you only read the memory block in one place and only write it in one place (the read and write can be in different loops or subVIs) there's no need for arbitration. By using two FIFOs you can keep them independent and avoid the conflict resolution code. See the help for "arbitration" for more details.

Rt / how can a fpga-bitfile be exchanged without recompile the rtexe?

Hello to all,
maybe someone of you knows the trick:
my program have two parts, one is running on RT-OS (LabView RT/PharLap) the other part is on a FPGA. For programming I'm using LV 8.5.1.
In the VI (on RT) which calls the FPGA, is a static path-reference on the bitfile. Idea of this was that the bitfile is dynamically loaded by every start of the RT and when there are bugfixes to do in the FPGA-code, then this could be done with an simple exchange of the bitfile (which I can send to the customer and he replaces then byself the file per FTP).
In fact replacing of the bitfile does not have any effect, it seems that the bitfile is integrated in the RTexe and so cannot be exchanged on harddisk. Only way to replace the bitfile seems to recompile the RTexe with the new bitfile.
Does anyone knows how this can be solved? Or is there no way to do so that a bitfile is loaded at runtime (as a file and not integrated in RTexe)?
Or is this maybe because the VI which calls the bitfile, is forced to be part of the compiled RTexe (build options)?
Greets,
Lars

Hi Lars,
as far as I know there are 2 ways to dynamically download a bitfile to an FPGA
device.
1. Using the NI-RIO driver (available at: http://joule.ni.com/nidu/cds/view/p/id/993/lang/en)
When you install the NI-RIO driver, the RIO Device Setup utility is installed,
which allows you to download bitfiles to the flash memory of your FPGA device.
After that when the device is reset or powerup, the device itself can load and
start this new bitfile. Just make sure that the option "Autoload VI on
device powerup" or "Autoload VI on device reboot" is set
accordingly under Device Settings in the RIO Device Setup utility. Change
these options of the device so that the bitfile is loaded on a reset or power
loss, then reset or cycle the power for the device.
2. Using the FPGA Target System Replication utility as discussed under: http://zone.ni.com/devzone/cda/tut/p/id/6465
With the help of the VIs included in this utility (http://digital.ni.com/public.nsf/websearch/AF4FF0C65AF31B4348257337006A144A?OpenDocument) you can basically set the same options and select a bitfile similar to the RIO
Device Setup utility of the NIO-RIO driver. Similar to the RIO Device Setup
utility you can download your bitfile to the flash memory of your FPGA and then
reset or power cycle your device.
I hope this information helps you.
Best regards,
Balazs

Crio multiple fpga vi

Hi,
I have constructed two fpga vi's for cRIO FPGA and tried to run them parallel in a host vi but when I run the host vi then the fpga vi's did not work properly.
I attach the vi's. What is the problem with these codes?
Attachments:
trigger.vi ‏57 KB
host.vi ‏375 KB
fpga1.vi ‏46 KB

Hi,
Unfortunately for you, this thread is correct and you can only have 1 LabVIEW FPGA VI running at a time.
However, here are some tips that may help you out:
It is possible to load different FPGA personalities during run time. Therefore, if you can separate your application into two different applications, you can load them on the FPGA while it is running ( only takes about 1 second to switch the FPGA to another personality)
Instead of putting the multiple FPGA VIs into a top level VI, have you tried to copy the block diagram from one into the other? In other words, combine them into a single VI with multiple parallel loops?
If you are having trouble with space on the FPGA after combining the FPGA block diagrams into one there are many documents online that will help you optimize the FPGA VI. For Example
Combine boolean indicators into a single U32( will save a significant amount of space)
Reduce the usage of arrays on your FPGA VI ( if you have them). There are other methods of storing this data such as a FIFO or the memory on the FPGA
Since you are using the digital only board and if memory serves me right, you can read the port instead of each boolean individually. This would save you some diagram space as well as some FPGA space.
Last but not least, consider contacting a systems integrator to assit with the development of your FPGA VI or the system as a whole. I know of one that does great work with FPGA's: www.viengineering.com .
Mike
V I Engineering

Parsing Boolean Array in FPGA

Hi All,
Although I have programmed in LabVIEW many times, I am quite a novice when it comes to programming on an FPGA, and I have been learning as I go (which up to this point has worked with little issue). However, I have been unable to resolve my latest issue, and the more I read about the FPGA, the less certain I am that what I am trying to do in even possible.
The task at hand involves reading in a set number of bits from the digital input/output lines of the FPGA and parsing these bits into specific words/"bytes." For the purposes of the VI that I have attached, I have faked reading in a set number of bits by supplying three 26-bit words (78 bits total) that have been been defined on the front panel. After supplying the specified bits, I am trying to parse the bit array into specific words that are given by the following logic:
1. Search for a start bit of 0 (false bit).
2. Once the start bit of 0 (false bit) is found the word that is trying to be parsed is the next 10 bits.
3. After the start bit and ten data bits is a stop bit of 1 (true bit).
4. Repeat steps 1-3, five additional times.
From the above logic, there should be six parsed words in total for the supplied VI. Unfortunately, I cannot simply take 12 bits (1 start bit, 10 data bits, and 1 stop bit) at a time, as the number of filler bits in between successive words is variable. The VI that I have supplied is one version of how I have proposed to accomplish the aforementioned logic, but I cannot compile the VI/project, as I continually receive errors that "Arrays must be fixed in size." To my knowledge, all the arrays in the VI have been preallocated and the logic seems deterministic.
If anyone has any suggestion as to why this VI is not compiling, I would be greatly appreciative. Thank you in advance for taking the time to look at this, and I look forward to resolving this issue.
With gratitude,
Gregory
Solved!
Go to Solution.
Attachments:
Example_Bit_Parser.vi ‏9 KB

Unfortunately, you're going to have to rework this VI to make it run on an FPGA. You can't relocate arrays in memory in an FPGA the way you can on a PC. You have a variable-sized array as the output of delete from array, because the length input isn't fixed at compile time. Also, two dimensional arrays aren't allowed. Remember that when you code for an FPGA you're actually writing the hardware - each value in an array is essentially a circuit (this is my overly-simplified understanding). The compiler can't allocate the right number of wires to carry an array if it can't determine the array size. The array isn't in memory so there's no way to rearrange it at run-time.
There are a couple of ways you could work around this, all of which will require iterating through every element in the input array. You could use an FPGA FIFO, and only put the values into the FIFO that are data (ie, loop until you hit a start bit, put the next 10 values into the FIFO). Then on the other side of the FIFO, possibly in a separate loop, read 10 bits at a time to get your data words. Another approach is to rearrange the array as you go. Keep track of the current location in the input array. Whenever you hit a start bit, move the next 10 bits (you may have to do this one at a time) to the current location in the input array, incrementing the current location each time. When you've finished all the input, all the data words will be at the beginning of the array in 10-bit units, which you can then split out as needed.

Loading 7831R memory with contents of Array from Host VI?

Hi,
Can anyone help - how can I load the contents of an array in the
labview Host VI into the memory of the FPGA on the 7831 board? When I
try to do this in a FOR loop, and index each element, it says that the
array must be a fixed size for this target. How do I do this? I
initialise the array in an earlier sequence frame, and am reading from
a local variable.
Thanks for any advice,
Joe.

In LabVIEW FPGA all arrays must have a fixed size, because they are allocated as static memory on the FPGA. As much as possible you should avoid allocating (large) arrays in your LabVIEW FPGA diagram since this will use a lot of FPGA space; about 1% of the FPGA for every 4 bytes of array data.
Instead of using an array in your diagram you can use the Memory Read and Write functions which provide access to 16kB of memory which is separate from the FPGA.
If you want to use an array as you described, you should create an array constant in your diagram or an array control on your front panel. To set the size, right click on the array index display and select 'Set Dimension Size'. Select the fixed size and specify the number of elements in the array.
T
o pass values to an array on the diagram use the 'Array Replace Subset' function on the existing array.
If you have an array control on your front panel you can directly pass the whole array from your host application to the FPGA VI and do not need to pass individual array elements.
Christian L
NI Consulting Services
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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FPGA code stops when RT code stops

I have developed some FPGA code to manage a piece of hardware. It's setup to read some default front-panel control configuration values and then sit there endlessly responding to signal inputs and producing signal outputs. The FPGA bitfile is written to flash memory so the FPGA loads and starts running almost immediately. So far all is good.
Next I layered onto the system (cRIO-9075) some RT code which opens an FPGA reference to the FPGA front panel and allows me to monitor a few indicators and change the configuration settings and cause the changed configuration settings to be used by the FPGA. So far this seems to work too when I run the RT code interactively (eventually there will be an interface to a host system).
The problem occurs when the RT code is commanded to stop. Stopping the RT code also causes the FPGA code to stop and I don't want the FPGA code to stop. The RT code does not make any calls to command that the FPGA code abort execution. When the RT code is stopped, the only thing it does with regard to the link to the FPGA is to close the FPGA VI reference that was opened when the RT code was started.
What do I need to be doing to cause the FPGA code to continue to run as the RT code is started and stopped?
Solved!
Go to Solution.

I'll have to wait until I get back to the office tomorrow to test this but I think this link has the answer to my problem.
http://lavag.org/topic/16412-confusion-regarding-fpga-deployment/#entry100294
It says: "the Close FPGA reference VI. If you right click you have an option to close or by default close and reset. This means the FPGA VI is reset (read aborted in standard LV speak) when we close the reference."

Quiero saber sobre Control de tranferencia de calor con PID

Hola Amigos quisiera saber si uno de ustedes tiene algun programa en Labviw 8.2 donde pueda controlar la temperatura con PID usando la DAQ 6008, si me puediesen ayudar le estaria muy agradecido y si no de alguna manera, gracias por su tiempo, nos vemos

Hola Antonio el control PID, es lo mismo si es para control de calor o nivel de un tanque o cualquier cosa, la diferencia radica en que la planta que controlas es diferente y por lo tanto los paramentaros cambian pero el principio es el mismo, por lo que puedes utilizar los ejemplos de PID en Help>>Find Examples para ver cómo puedes utilizar. La forma más fácil de realizarlo es si tienes el toolkit de control PID
Este foro te podría ser de interés:
http://forums.ni.com/ni/board/message?board.id=6170&message.id=1932
En esta liga puedes encontrar en español un poco de información sobre lo que es PID.
http://es.wikipedia.org/wiki/Proporcional_integral_derivativo.
También estos links te pueden ser de gran utilidad:
Ready-to-Run PID Temperature Controller
PID Theory Explained
Using the LabVIEW PID Control Toolkit with the LabVIEW Control Design and Simulation Module
PID Control
Complete resources for a PID control system with NI M Series devices
PID control
Configuring a Non-Linear Process Control System using National Instruments Products
Con respecto a los parámetros específicos que debes de usar dependen completamente de tu planta (sistema térmico a controlar)
Saludos
Benjamin C
Senior Systems Engineer // CLA // CLED // CTD

Memoria Agotada

Hola buenas tardes,
Actualmene cuando ejecuto un reporte en SBO y el mismo genera mucho registros el sistema me muestra un mensaje de error indicandome memoria agotada (odbc-100), esto sucede cuando intento ejecutar el reporte en vista preliminar y en PDF.
Alguien me podria ayudar?.
Estuve leyendo algo sobre la memoria AWE, pero como mi servidor es 64 bits no aplica.
Saludos,

Hola.
El tamaño del log es demasiado grande respecto a la base de datos y por supuesto afecta el desempeño del sistema.
Te aconsejo seguir las recomendaciones de SAP que vienen en la Guía de administración.
Puedes comenzar intentando cambiar el modelo de recuperación de la BD a SIMPLE. Esto debe mejorar el rendimiento notablemente.
Además puedes ver muchos otros casos en el foro que tratan el tema de performance o desempeño, como los siguientes:
- Mejorar rendimiento SAP 8.81.
- Re: BLOQUEO DEL SISTEMA AL GENERAR REPORTES DE GRAN DEMANADA.
Saludos.

FPGA array

I am using PXI 7833R which has 3M gate reconfigurable I/O (RIO) FPGA with 190 kB of embedded RAM.
Now I want to build an array with 3000000 elements, is that possible?
My test pattern is in form of .txt file, how can I send this data to the FPGA array through the Host? It seems that I can not write an array control from the Host to the FPGA through the "Write and Read Function" . Is there any good way to do this?
Thanks

Using the 3M gate FPGA you can not store an array with 3,000,000 elements. The best option is to use the 192 kB of memory but that will not be enough for what you describe.
If you try to implement an array in LV FPGA which will be implemented on the FPGA, you will only be able to allocate a few hundred elements, because implementing data storage on the FPGA is very inefficient.
In general you can implement small arrays on the front panel of the FPGA VI and read or write them using the Read/Write node from the host VI.
Depending on how fast you need to output your test pattern, you may be able to store the data in the host VI and stream it to the FPGA as it is being generated. You can use the 192 kB of memory on the FPGA to buffer the data between stream from the host and outputing from the FPGA.
Can you provide more details about your applications? How fast do you need to generate the data? Digital or analog? Will this buffer be generated once or be repeated? Is your host application running in Windows or LabVIEW Real-Time?
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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Digilent Nexys4 - programming the SPI FLASH with an FPGA configuration file

I made a short video of my notes once I eventually figured out how to do this. This video shows how to program the on-board SPI Quad Mode FLASH memory with an FPGA configuration file using iMPACT in ISE.
https://youtu.be/-KORahDVVrk
I hope this is not spam - please just ignore if not helpful!

There is Application note for the same in detail.
http://www.xilinx.com/support/documentation/application_notes/xapp586-spi-flash.pdf

Adding FPGA reference causes problems

Hi,
I have a programme which runs on the RT engine and calls up an FPGA reference, samples data from this and then carries out some calculations on it. I'm currently trying to modify this to add more functionality, but have hit a problem. The picture attached is the original programme which works fine, but when I add another "Open FPGA VI reference" above the one shown, which is targeted to the same PXI 7833R card, but calls a different VI, it causes the original code to stop running properly. I haven't been able to track down the root of the problem, but it appears to be affecting the sampling of data in the original programme. I'm thinking it is something to do with timing as I haven't changed a single part of the programme except adding this extra FPGA reference, so all I think it could be affecting is the speed the programme runs at.
Does anyone know of any problems associated with opening two FPGA references at once?
Just in case you need to know, I'm running Labview 7.1, with a PXI 1042 chassis, PXI 8186 controller, PXI 7833R FPGA card and PXI 8461 CAN card.
Thanks,
Nick
Attachments:
working.jpg ‏73 KB

Nick,
As you add more code to the FPGA VI it will take longer to compile. If you get close to filling up the FPGA the compile time may increase significantly as the compiler spends more time to optimize the code that is generated to fit onto the FPGA.
Using large arrays on the front panel of the main VI or anywhere within your VIs will increase the size of the code and increase the compile time.
There are different ways to get around using large arrays but it is difficult to recommend a specific solution without knowing more about your application. All of these solutions will use the block memory available on the FPGA to store the data in one way or another. You should probably look at using FIFOs if you stream the data between the host and FPGA. Using FIFOs you can pass one data value at a time between host and FPGA, reading them from or writing them to the FIFO. You will need some form of handshaking to synchronize the host/FPGA communication.
An alternative is to use the DMA FIFOs which will further simplify the communication between host and FPGA.
If you want to pass blocks of data to the FPGA so that the data can be accessed repeatedly (like a lookup table) then you should use memory blocks on the FPGA to store your data. That provides random access by address to a predefined block of the memory on the FPGA.
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
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Informaciòn sobre la memoria de la FPGA

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