Inter-SLR compensation in Synthesis Timing Report

Question

2015.1 targetting xcku115
The timing report out of synthesis is showing huge intra-clock hold time violations of up to -1.406 ns, 500,000 failing endpoints. These errors show for pretty much all clock domains, both fast and slow clocks. 
'View path report' shows inter-SLR compensation on these failing nets. Why does Synthesis assume these nets will all be crossing between die? The current netlist fits nicely all into single die with all the IOs. I have a pblock constraining everything to one die and the timing report mentions that pblock too.
Are there any directives to use that can guide synthesis better in this scenario?
-bisector

Answer 1

Inter-SLR Compensation (inter-SLR penalty) is applied to compensate for any possible PVT differences between SLRs in SSI devices.
A simple rule is that if either the clock paths or data path crosses the interposer, the path should be penalized,
except for some special clocking scenarios (e.g. clock is common to the same SLR).
In this example, the data path goes out of the SLR and then comes back.
Therefore, Inter-SLR Compensation is applied even though the source and destination are in the same SLR.