Problems with IO timing constraints

Question

I am developing a system for Virtex-6 FPGA under ISE environment.
Now I have several I/O pins that need to be constrained in timing.
I have an overall system clock called sys_clk in 100MHz, and a logic-generated clock called sr_clk in 125MHz.
I need to make offset constraints referring to sr_clk. However, it seems that the constraint editor will only recognize sys_clk. Any constraints with sr_clk reference are invalid.
How could I solve such problem?

Answer 1

Thanks 
I have tried the following statements in my ucf file:
NET "sys_clk_n" LOC = T7 | TNM_NET = "SYSCLK";
NET "sys_clk_p" LOC = T8 | TNM_NET = "SYSCLK";
TIMESPEC TS_SYSCLK  = PERIOD "SYSCLK" 100 MHz HIGH 50 % PRIORITY 100 ;
NET "sr1_clk_out" LOC = AR20 | TNM_NET = SRAM_CLK;
NET "sr2_clk_out" LOC = AW16 | TNM_NET = SRAM_CLK;
TIMESPEC TS_SRAM_CLK = PERIOD "SRAM_CLK" 125MHz HIGH 50% PRIORITY 100 ;
TIMEGRP "SRAM_DATAADDR" OFFSET = IN 2 ns AFTER "sr1_clk_out" HIGH;
TIMEGRP "SRAM_DATAADDR" OFFSET = OUT 2 ns BEFORE "sr1_clk_out" HIGH;
The final timing report after P&R shows that there are 0 paths analysed for last 3 constraints during the process.