Internal clock timed aquisition with DAQmx

Hello,
Im have just begun using DAQmx and have little experience with DAQ Hardware. I have a requirement to do data aquisition across ~10 analog channels at 1kHz. I have looked at the DAQmx examples (specifically 'Cont Aqc&Chart Samples - Int Clk') and as I understand, one can do a 1kHz aquisition using the internal clock? What kind of determinism is expected using the internal clock? I have my loop running with a 20ms wait, reading 100 samples at 1kHZ. Is this adequate?
Secondly, can you do a triggered stop on analog reads (just as you can do a triggered start?).
Thanks,
David
Im using a PCI-6221 card with LV 7.1, DAQmx 7.3.0.

The determinism of the board clocking in your data is extremely good. The determinism of your software (i.e. algorithms, waits, etc) is unknown and you are at the mercy of SW jitter. I think the specs you provided should be adequate, but if you start running into buffer overflow problems you will have to decrease your wait, read more samples, or setup a bigger buffer. If you need true determinism then you should be using LabVIEW Real-Time, but it seems like for this application it would be overkill.
Stuart

Similar Messages

Timing features with DAQmx

This is my first big labview programming endeavor and I am ready for the DAQ portion of the program.
I created the following code to acquire X-seconds of data @ sample rate. And display elapsed time and % fill bar.
I want the Channel indicators to refresh as data is acquired, so I setup DAQmx to acquire 1 sample in a timed while loop.
I set up the flat sequence structures so I could measure the actual test duration.
As is shown a 5 second test takes 5.057 sec’s.
100s=100.205
Eventually the time will be significant, and I’m worried when I start sampling more than 1 channel the time will be compounded.
Any suggestions for code improvement?
Attachments:
RECORD.png ‏151 KB

Just a few observations (#1 is really the most important takeaway):
1. Running your loop at 500 Hz (or beyond?) isn't what you really want. Assuming you do want to sample at this rate, you'd be much better off using the N Samples variant of DAQmx Read. N should be whatever makes your loop run at a reasonable rate (5-10 Hz should be plenty for the purposes of updating the few front panel indicators). For example, at a 500 Hz sample rate, reading 100 samples per loop would make the loop run 5x per second.
1b. With this change made, you'll find that the read now returns a 1D array of values that you will need to insert into a single longer 1D array. It is optimal to pre-allocate this longer array rather than appending to it on every loop iteration (i.e. Initialize the longer array to the correct size outside the loop and use the Replace Array Subset inside the loop).
2. You may take out the wait function--its purpose is to keep the loop from running unchecked and consuming CPU. The DAQmx Read call blocks until data is available and already does this for you. At best, the wait is redundant (if it is less than or equal to the time that the DAQmx Read blocks, it does nothing). At worst, the wait will lead to a buffer overflow (if it prevents the read from executing at the speed it needs to).
3. This probably won't even be noticeable, but... if possible use the front panel terminals themselves when updating indicators inside your loop (right now you are using value property nodes which forces an immediate redraw). If not, use local variables instead of the value property nodes.
4. You could pull some of the math outside your loop (division is pretty expensive) but it won't make any noticeable difference once your loop is running at a reasonable rate.
5. This won't affect performance at all, but I found this portion of the block diagram's wiring to be very confusing:
Also, usually I try to create a DAQ task exactly one time in a program if possible (during an initialization routine)--here it looks like you're creating it every time you want to start recording. If you create the task once and then start/stop it as necessary you'll shave some ms off of your benchmark (quite possibly not worth the trouble though, depending on what the rest of your applicaiton looks like).
Best Regards,
John Passiak

US event timing with DaqMX help

Greetings. My Labview experience has been largely cFP and cRIO so my DaqMX experience is limited. I have a program for my PCIe-6353 that will operate like this:
DO1 high
wait a period as low as 700 uS
DO2 and DO 3 high
wait 700 uS
DO3 low DO4 high
Take analog voltage data at 40 kHz
DO2 low
DO1 low
This is all quite simple but I am not sure what architecture to use for the timing. Any ideas or examples would be helpful and greatly appreciated. I have been playing with using multiple timed sequences with different offsets but not sure if this is the best way. I'm spoiled with the FPGA pallette where I can just drop a uS delay and move on.
Thank you for any input you may have.
Dave B
www.signalg.com

Hi Dave,
I think that you would have better luck on the Multifunction DAQ forum. But to address your issue, there are a couple ways to do that. First, you could do a Digital Output using a 10kHz clock on your 4 lines. For this, you could use an example like "Write Dig Chan-Int Clk-Dig Start.vi" found in the NI Example Finder under Hardware Input/Output»DAQmx»Digital Generation. That example would need to be modified to include the waveform that you've built (either from a waveform constant, or from the Digial Waveform Editor).
Is this generally what your timing diagram would look like?:
Your other option would be to use 4 counters. Hopefully that gets you started- let me know what you're interested in pursuing. But again, I would recommend migrating this post to the DAQ forum. Have a good one!
aNItaB
Applications Engineer
National Instruments
Digital Multimeters

I got Internal Software Error -223044 with my PXI-4472, PXI-1033 and NI expresscard-8360 DaqMx 8.8

When i running the self test of the board in MAX i got error -223044, anyone that has some ideas??
STALT

Hey Stalt,
This particular internal error begs me ask a few questions.
1) Has this 4472 ever been used with DAQmx?
2) How old is this 4472? When was it bought from NI? Can you give me the revision letter of the board? That is found by looking for a number printed on the board that usually begins with "ASSY", then there are several other numbers/letters, but the one letter I care about is the letter right before the "-" So it would look like ASSY11111111E-01 so the revision would be "E"
3) Do you have another PXI system (with DAQmx) that you can initialize this 4472 in?
Let me know
-gaving
Software Engineer
National Instruments

If I configure a buffered pattern input and a buffered pattern output on the 6534 to both operate from the internal clock, will data be transferred out on the same rising edge as data is transfered in or are there two separate oscillators?

Basically, I want to perform a buffered pattern output synchronously with a buffered pattern input. If I configure the two groups to be internally timed from the same frequency, will the data in be transferred on the same edge as the data out or will the two groups use different oscillators?

Hi Joseph,
There are two clocking structures on the 653x boards, one for each group. This means, even if you specify the exact same frequency for both there is no guarantees that they will be synchronized exactly.
The workaround for synchronizing both groups is to have 1 group clocked internally and 1 group to be clocked externally. Then route the Req line from the internally clocked group to the Req line of the externally clocked group.
Hope that helps.
Ron

IPod Nano International Clock Settings

I live in India and recently bought an iPod Nano. I wanted to use the International Clocks but the timing listed for the European cities as well as the Asian cities is wrong by exactly half an hour ahead of the real time.
Apple India are saying there is nothing they can do as there is no option to change manually the time on the listed cities. My Nano shows the correct time as I entered it manually, but I wanted to get some of the European cities as well.
Does anyone know how to solve the problem???

Could be something to do with Daylight Saving Time. Set the clock to the "wrong" time then select daylight saving time and adjust it either on or off, this could change the time. Other than that, send it in for a service.

External clock LabView crash with Measurment Computing board.

Hi,
I'm using a Measurment Computing PCI-DAS6402-16 board with Labview (using Universal librarys VIs) in a 4-stroke engine DAQ application and amognst the signals obtain Internaly clocked, there is In-Cylinders Pressure signal which is timed with a Crank-angle deocoder sending analog pulse signal.
Although there seems to be no problem while the motor is running, it appears that when to external clocked signal is not getting any pulses (while the motor is not running) then Labview stops to respond and awaits for the external clock to start, and that doesnt happen within 10s then it crashes.
I dont know whether it is Software problem (because external and internal clocked signals are both in the same WHILE LOOP) or if it is a Hardware problem (because With a NI card there seem to be no problems).
THNX in Advance

Well it couldnt be a more typcal windows crash:
If a channel is externally timed with an analog pusle signal, If the VI starts running but the external clock isn't then:
-Labview stops to respond to any clicks (there is no .exe at this point) but it keeps working though (That i know cause if i start the ext. clock at this point it "un-stucks' and starts working)
-But, if for some secs no ext. pulse signal is generated then labnview app stops respondin and i get the typical 'send error report' window.
Could it be that the Universal library for Measurment Computing boards haw a bug? Cause the same thing happens with the "Analog input External Clock.vi" example given with the Library..so it can't be my mistake..or can it?!

Computer shuts off when unplugged, resets internal clock

I have been having an issue lately with my mid 2009 MBP 13in where occasionally if the magsafe adapter is removed from the notebook, it will suddenly shut off. After about a minute, I am able to start it up again and it will be on battery power until I reset the SMC. When it does load up OSX, the internal clock is reset to some date in 2001 and I have to manually change it back to the present for everything to play nice again. It's been pretty annoying at times and I have no idea what would cause the computer to act up so sporadically. I can't recreate the problem on command, it just happens when I least expect it. The battery is fine as Coconutbattery shows a life of about 89% still. Does anyone have any idea what and why this occurs?

Remove the battery and inspect for any abnormalities. Check the contacts on both the battery and the computer. Also check your battery status under Apple Menu> About This Mac. Click on More Info and then the System Profiler will come up. In the left hand column select Power and see what your battery status is there compared to what Coconut battery said.

Pulse Generation application with DAQmx and a PXI-6624 module?

What is the best implementation method for the following pulse generation application
using LabVIEW, DAQmx and a PXI-6624 counter\timer module?
I have two rising edge trigger signals (Trigger-1 and Trigger-2).
There is ample spacing between each trigger. They never occur at the same time.
I need to generate a single pulse (fixed width, variable delay) whenever Trigger-1 occurs and
a finite pulse train (fixed width, variable delay, N-pulses) whenever Trigger-2 occurs.
However, the output must appear on one counter output because this composite signal
will be used as a trigger source for another PXI module in the rack.
With DAQmx and a TIO counter\timer can I use both the GATE (for Trigger-1) and
AUX (for Trigger-2) at the same time on the same counter to gate out the desired pulses?
Trigger-1 would be wired to the GATE of CTR0. One Trigger-1 event would generate one pulse on the output of CTR0.
Trigger-2 would be wired to the GATE of CTR1 and the output of CTR1 would be routed to the AUX input of CTR0.
One Trigger-2 event at the GATE of CTR1 would generate multiple pulses on output of CTR0.
Would DAQmx and the PXI-6624 TIO support this implementation?
What is the best way to accomplish the task at hand.
Thank You.
Best Regards,
Scooby

Hi Scooby,
I have looked into the application you have described and I see a potential problem with what you describe. In DAQmx, it is not possible to call the counters of the same DAQ device in the same task, so you cannot have the finite pulse train generation and the single pulse generation tasks running at the same time. What you can do, since you mention the triggers will not occur at the same time, is to stop one counter task while you are triggering another. The way I would suggest you merge the outputs is with a two input Or logic gate to avoid damaging your counters. Your signals will effectively be added together by this logic gate. I do not see any way to merge the outputs internal to the DAQ device.
Please let me know if I can be of additional assistance.
Laura

How to generate sequence of pulse trains with DAQmx?

I need to generate a sequence of pulse trains with DAQmx (the card I have is a PXI-6229 card). As an example:
- 10'000 pulses at 20kHz every 5 seconds with an initial offset of 2 seconds (let's say 10 pulse trains in total).
If I use the CreateVirtualChannel.vi in "CO pulse ticks" mode, I can only specificy offset, high ticks and low ticks, but not that the sequence of pulses should be repeated after some time.
Now I thought that I could solve this problem if it were possible to multiply two counter outputs: the first counter would generate the pulses (continuously) whereas the second one would switch between low and high on a slower timescale in order to gate the first counter, thereby providing an initial offset and the "off" phases between the pulse trains.
Is it somehow possible to multiply two outputs with DAQmx and the card I have? Or is there another solution to the problem?
Thanks a lot in advance for any hints!

Hi dlanger,
what you want to do requires a little bit more work.
First look at the example "Gen Dig Pulse Train-Continuous.vi" from the LV example finder.
This example generates a continuous* pulse train. As you see, you need a sample clock VI for setting the sample mode.
* NOTE: Generating a finite pulse train with a M-series card requires 2 counter.
With a pause trigger (DAQmx trigger property node) you can gate the output of that counter.
Now you have to generate a gate-signal with the the 2nd counter. That means, only if Ctr1-out is high Ctr0-out outputs the 20 kHz-signal.
Maybe you have to adjust the times in my example a bit.
Unfortunately there is just one "small" problem: "let's say 10 pulse trains in total"
This is not possible, because a 3rd counter would be necessary (*).
As a workaround you can modify the while-loop that both tasks are cleared after 50s. This is not brilliant, but should work fine for you.
A more sophisticated way is to perform a correlated DIO. So you can generate custom pattern for multiple outputs.
A good example can you find here:
Retrigger and Repeat Finite Digital Pulse Train in LabVIEW
http://decibel.ni.com/content/docs/DOC-8473
or here:
Generating More Than 2 Pulse Trains Using CompactDAQ
http://decibel.ni.com/content/docs/DOC-2167
Hope this helps.
With best wishes,
Ralf N.
Attachments:
Gen Gated Dig Pulse Train-Continuous.vi ‏38 KB

Error -200141 when doing buffered events with DAQmx and PCI-6602

When doing buffered events with DAQmx and PCI-6602 I get error 200141 - Data was overwritten before it could be read by the system.
This error is generated ONLY with random inputs >200/sec.
My setup is :
DAQmxCreateCIVCountEdges(taskhandle,"Dev1/ctr3"....
DAQmxCG+FGSampClkTiming(taskhandle,"/Dev1/FPI35",...
DAQmxSetCICountEgdesChan(taskhandlem,"", "/Dev1/80MHZTimeBase")
DAQmxSetChanAttribute(taskhandlw,",",DAQmx_CI_DataXferMech,DAQmx_Val_DMA,0);
Can somebody help ?

i'm getting the same Error-200141, while reading semiperiods. (Meas_Buffered semiperiod continous)
while loop ex.rate seems to be pulsewidth*no.Samples to read. in my case PW=60ms
Input buffer size measured with Property node= 10000
why this error happens?? i cant use any mode other than implicit timing for semi-period measurement right??
more info: all the ai channels are used ~ 16 differencial.
i found one solution which is _ reinitializing the whole task if an error occur. is this the right way??
Kudos always welcome for helpful posts
Attachments:
Counter_1_Meas Buffered Semi-Period-Continuous_main_lv09.vi ‏34 KB
SemiPeriod_Reconnect Counter on Error.vi ‏35 KB

HLS creates internal clock enable??

In HLS (2015.2), I created a simple comparator circuit. The HLS C-simulation worked fine.
The HLS C-function compares 8-bit integers received from an 8-bit data bus against a fixed array
of 8-bit integers. If the first integer matches, a counter is incremented, and the C-function
will then look for the 2nd integer in the array. If the sequence of 8-bit integers on the data
bus matches the sequence of bytes in the stored array (distributed memory Eg. ROM), a match
is detected.
After observing a good C-simulation, I then instantiated the HLS Verilog file code into the actual
hardware, and attempted a Modelsim simulation. It did not work!! This is a very simple circuit. The
Verilog file has the ports below.
ap_clk
ap_rst
ap_start
ch(7:0) <--- This is the incoming 8-bit data bus.
ch_valid
ap_return <--- This is the match signal.
If ch_valid is HIGH, the comparator should compare ch(7:0), against the known internal fixed array of 8-bit
integers. The signal ch(7:0) changes every ap_clk. The problem with the hardware is that HLS
created an internal clock enable. For this circuit to work, the ch(7:0) bus needs to be stable for
2-clock cycles. The only reason I found this was because saw what was happening in ModelSim.
When coding in C, there is no concept of clock. I thought HLS was intended to allow the user to create
code and to not be concerned with clocks and other hardware events.
Questions:
1. Is the purpose of HLS to allow a software programmer to be able code and create hardware, or does an HLS
programmer need a hardware background?
2. If the HLS programmer does not need a hardware background, how would a software programmer find
an internal clock enable?
3. Is there a switch to prevent HLS from creating code that uses internal clock enables, or does the C-code
need to written in a certain way?
Thanks!

In HLS (2015.2), I created a simple comparator circuit. The HLS C-simulation worked fine.
The HLS C-function compares 8-bit integers received from an 8-bit data bus against a fixed array
of 8-bit integers. If the first integer matches, a counter is incremented, and the C-function
will then look for the 2nd integer in the array. If the sequence of 8-bit integers on the data
bus matches the sequence of bytes in the stored array (distributed memory Eg. ROM), a match
is detected.
After observing a good C-simulation, I then instantiated the HLS Verilog file code into the actual
hardware, and attempted a Modelsim simulation. It did not work!! This is a very simple circuit. The
Verilog file has the ports below.
ap_clk
ap_rst
ap_start
ch(7:0) <--- This is the incoming 8-bit data bus.
ch_valid
ap_return <--- This is the match signal.
If ch_valid is HIGH, the comparator should compare ch(7:0), against the known internal fixed array of 8-bit
integers. The signal ch(7:0) changes every ap_clk. The problem with the hardware is that HLS
created an internal clock enable. For this circuit to work, the ch(7:0) bus needs to be stable for
2-clock cycles. The only reason I found this was because saw what was happening in ModelSim.
When coding in C, there is no concept of clock. I thought HLS was intended to allow the user to create
code and to not be concerned with clocks and other hardware events.
Questions:
1. Is the purpose of HLS to allow a software programmer to be able code and create hardware, or does an HLS
programmer need a hardware background?
2. If the HLS programmer does not need a hardware background, how would a software programmer find
an internal clock enable?
3. Is there a switch to prevent HLS from creating code that uses internal clock enables, or does the C-code
need to written in a certain way?
Thanks!

An issue with DAQmx Error messages

Greetings,
I'm using a 6602 counter board with DAQmx 7.4, ANSI C API. A strange issue concerning the errors due to faulty attribute values keeps occuring, that being no error is reported when the (faulty) attribute value is set but only when it is read back afterwards. Shouldn't the faulty value be reported by the Set function?
To be specific, I'm creating a period measurement counter input channel with implicit timing, sample mode = finite, then setting the number of samples per channel to 0 (bear with me, I know the 0 value makes no sense here, the point is how the errors are being reported so that they can be handled in a reliable and consistent way). While DAQmxSetSampQuantSampPerChan(taskHandle, 0) does not produce an error, calling DAQmxGetSampQuantSampPerChan(taskHandle, &SampPerChan) for verification on the very next line returns Error -200077 : "Requested value is not a supported value for this property". So, my question is why the error is reported by the Getter instead of the Setter? Is this normal behavior (if so why?) or is something amiss here?
Jeff

This is the expected behavior. Validating attributes is tricky when attributes are dependent upon other attributes. There are two main approaches that can be taken by NI-DAQmx.
One, when every attribute is set, NI-DAQmx could verify the value of that attribute in the context of the task (i.e., in the context of all other attributes). This is problematic for at least a couple of reasons. One, validating the task after every attribute is set is time consuming and not efficient. Two, validating the task after every attribute is set requires that customers set attributes in a specific order such that dependent attributes are set after their dependencies. This would dramatically decrease the usability of NI-DAQmx. In fact, if attributes are mutually dependent, this approach is impossible.
The second approach is that NI-DAQmx doesn't verify the task until it is forced to do so. Starting a task forces it to be validated. Querying an attribute also forces the task to be verified since the value of an attribute may be dependent upon the value of another attribute.
As you've noticed, we've taken the second approach with NI-DAQmx. This approach leads to a more efficient execution as well as allow customers to set attributes in an arbitrary order. If you want to force the task to be verified in order to check for errors, you can do so explicitly at the desired time. However, the need to check attributes for errors is most often needed when the application is under development and the NI-DAQmx error reporting features makes it easy to determine which attribute has been set to an invalid value even when that error is not reported immediately.
Now, in reality, the way NI-DAQmx handles attributes is a bit more complicated than what I just described. Since some attributes are not dependent on other attributes or, since some attribute values can never be valid regardless of the values of other attributes, these attributes are verified when they are set and errors are returned immediately. We refer to this as coarse attribute verification. For example, if you set the sample rate to 100 MHz on an E-Series device you will immediately get an error.
Hope this helps clarify the behavior.
geoff
Geoffrey Schmit
Fermi National Accelerator Laborary

OS-X internal clock isn't working

All of a sudden I'm getting an error message when I start up my iBook about my internal clock. The past 3-4 weeks I keep getting a message that my internal clock is set prior to 2001 and may cause problems. I'm not quite sure what internal clock it is talking about, but have been having problems with some things that are attached to a specific date. Even my battery doesn't seem to work right. In the past I got a warning that I was below a certain amount of battery charge, usually some where around 10%-13% of charge left. Now, the gauge will sometimes show as much as 30% of the battery and my iBook will shut down.
Whether or not the problem with the internal clock has anything to do with the battery I don't know.
Does anyone know what kind of "internal clock" the error message is talking about?

atomicluck1 wrote:
Michael, thank you for the link. Question now is how do I figure out which iBook I have?
OK, start here:
iBook: How to Identify iBook Models
Note the different typeface (Apple Garamond) used on the earlier models, illustrated at the top of each table.
You can also do Apple Menu > About This Mac and then click on the "More Info" button to get to the System Profiler. As it happens, my iBook is officially a "Late 2001" rather than a true "Dual USB", but among other things System Profiler says:
Machine Name: iBook
Machine Model: PowerBook4,1
CPU Type: PowerPC 750 (33.11)
Number Of CPUs: 1
CPU Speed: 600 MHz
Boot ROM Version: 4.2.7f1
If you post your equivalent information (leave out your serial number) somebody will be able to decipher it.

Precision of internal clock of BNC-2110

Hello, I am using the BNC-2110 to get some measurement.
I am working with the presion ot 10000 datapoints each second.
But during a measurement of 30 seconds (external clock) I just get 299970 datapoints, insteads of 300000! So there are missing 30 datapoint. During a measurement of 5 seconds there are missing 5 datapoints.
Could it be a inaccuracy of the internal clock of the BNC-2110?
Thank you for your help.
Rest regards, AlexJ

Hello, you are right with your assumption.
I did some more measurement and got some interesting results:
I calculated the difference of two sinus-signals of the same frequency. The data-points of one of them I got from MatLab, the other one I measured with the BNC from NI
I used a toolbox from NI for MatLab and used the order
AcqNUpdates('Dev2/ai0:7', -10, 10, 100000, 10000, 2);
Do you know this toolbox?
The plot of the result of the difference can be seen in the atachment.
I think the sudden changes of the difference every second (t1=0.75 t2=1.75) is the result of the missing datapoint mentioned above.
I got this result with several measurements and with every channel.
Did somebody else already had this problem?
Best regards, AlexJ
Attachments:
Diff_Verfahren4.JPG ‏14 KB

Internal clock timed aquisition with DAQmx

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