LabVIEW FPGA PMW modulation for L298n H-bridge

Hello to everyone,
I am new in LabVIEW FPGA programing and I have a couple questions, so I would be grateful if you could answer me. For my final work I have to control the speed and direction of DC motor using sb-RIO 9636 and H-bridge L298n. In attachments you can find scheme of the H- bridge and my program. I have conected In1(pin 5 of L298n) to digital pin 1 of the card, In2(pin 7 of L298n) to digital pin 2 of the card and changing the state of the pin I change the direction of the motor(I know that the one In should be Low and the other High so the motor can rotate in one or the other direction). PWM(Enable pin of the L298n pin 6) I have conected to DIO3.
PWM signal I cretaed is shown in picture.
My questions are:
1.Will loop timer I used, provide that period of signal is lenght I specify in the control(for example if I put 20 000 will the period be 20000 s)?
2. Can I vary the duty cycle changing the control Waiting (DIO3 is HIGH for a couple of us, then it sets LOW, and then all that repeats )?
3. Earlier I thaugt that PWM signal I should send in both IN1 and IN2, and that the Enable pin is used to stop or start the motor. I tried that and the motor was rotating different speed, and I could stop or star the motor with enable pin, sending it HIGH OR LOW, but I could not change the direction of the motor. So my other option was to conect the pins as I explained at the begining. My question is: Should I PWM conect to the enable pin, and will thah work?
Thank you

I found a couple of resources that deal with PWM on the FPGA and motor control - they might be helpful to reference as you look for answers to your questions.
Developing a PWM Interface using LabVIEW FPGA
http://www.ni.com/white-paper/3254/en/
CompactRIO Motor Control Basics Tutorial
http://www.ni.com/pdf/labview/us/compactrio_motor_control_basics.pdf
PWM Output With LabVIEW FPGA
http://www.ni.com/example/26499/en/

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Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
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Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
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LabVIEW FPGA PMW modulation for L298n H-bridge

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