Labview vs Xilinx controller on FPGA

Hi,
I have a FPGA : Processor Xilinx XC2S30
and platform : Digilent, Digilab 2XL
Is labview compatible in some ways ?
If yes how ? and,
What Labview can do better than Xilinx (simulink, Matlab)?
If no, what Platform I can use ?
CompactRio seems to be heavy ?
What avantages I can have with this configuration ?
Many Thx
Paul

Nicola:
I can't really speak to your hardware (it isn't going to be officially supported), but if the functionality you need is implemented in the .dll that ships with your board, you could potentially use LabVIEW to call and use the .dll.
Just bear in mind that the hardware interaction has to happen through the .dll, as there isn't any direct support for that hardware in LabVIEW.
Good luck!
Caleb Harris
National Instruments | Mechanical Engineer | http://www.ni.com/support

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Xilinx Options in FPGA Target Properties not available

Hello Everyone......I have a little problem.
I can not get Xilinx Options under FPGA Target Propoerties to change the synthesis optimization goal to area instead of speed in LabVIEW 2012. Please let me know the cause and solution of this problem.
Thank You.
Solved!
Go to Solution.

chiks,
Interesting, are you looking in the correct place for the compiler options? Compiler options aren't going to be located under "FPGA Target Properties" as you mentioned previously (sorry I missed this in your first post), rather those options are located under the "Xilinx Options" category when you create an FPGA build spec for compilation.
Right-click on Build Specifications » New » Compilation, then select the Xilinx Options category and you should see a window like this.
Can you confirm that you are looking in this location?
Nick C | Staff LabVIEW Platform Product Support Engineer | National Instruments

Is the labview 8.2 compatible with FPGA (altera) thats ordering code is DK-DSP-3C120N ?

is the labview 8.2 compatible with FPGA (altera) thats ordering code is DK-DSP-3C120N ?

Hey Mouath,
The FPGA module only supports the following:
Virtex-II 3000
Virtex-II 1000
Spartan-3 1000
Spartan-3 2000
Virtex-5 LX30
Virtex-5 LX50
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Please refer to FPGAs - Under the Hood for further information.
Aashish M
Applications Engineer
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http://www.ni.com/support/

Labview error GPIB controller not adressed correctly

I get this Labview error: GPIB controller not adressed correctly (LV5.1, win NT4) when i try to send data to a HP4275A LCR meter. How ever it works on an older system running with LabView 5.0 (also NT)!!!
How can I get rid of this problem????

Hi Diego, thanks for the hints!
I tried to configure (GPIB) everything standard.
when I try a 488 command initialze, I get the controller conflict, when i don't do this I get atime out problem either by 488 write-command or by 488.2 send-command.
the differences between the systems where it works and where not are:
working: Win 95, LV 5.0, GPIB-card/TNT (plug & play)
not-working: WinNT, LV 5.1, GPIB-card/PCI
i tried to set baord config to the same parameters...
on the faulti system however I see the instrument with the MAX and I can send commands, without problems !!!!
Also the driver you posted does not work (but the NI-communicate program ;-)
i have no clue what else to do!
btw. how do I copy the spy output when running the program? I may provide
this to find errors.
Since MAX indicates the board is all right I guess it is not necessary to reinstall the boarddrivers?!

Does LabView 2013 supports spartan 3E FPGA

Hi,
whether Labview 2013 supports spartan 3E driver.
i could not able to find drivers for that.
Else, i have procured Xilinx XUP V5 board.
can i use the virtex 5 board with labview 2013. for that any driver is there...

T-REX$ wrote:
Hey mangood,
There currently is no support for the Spartan3E board in LabVIEW FPGA 2013, and I am not aware of any plan for developing support in the near future. Sorry for the bad news...
DEAR
i have lab view 2012 and it has device drvie for spartan FPGA
only one year
may be can NI do this its simple
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Is there a way to download firmware from a Labview GUI to an Actel FPGA or a ARM Processor?

I dont know if it is possible but i have a couple of test that need to be done where multiple firmware is requiered to be downloaded to the pcb. So everytime i need to go and open Flash Pro(microsemi) and download firmware to the Actel FPGA and then go back to labview. I wonder if there is a way to do that from my labview Vi so that firmware will download automatically?
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Solved!
Go to Solution.

You should be able to make TCL scripts inside of your Flash Pro software. They have a macro generator that will just mimic what you do. Save off that TCL file. You can then load Flash Pro using the System Exec with a parameter pointing to that script file. Flash Pro will then run that script and close when done.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines
Attachments:
Call TCL Script.png ‏20 KB

New App Note explains how to program Xilinx 7 series FPGA's eFUSEs on a device programmer

Xilinx 7 series devices contain one-time-programmable eFUSEs to hold the encryption key for on-chip AES encryption/decryption as well as a 32-bit, user-defined value that can be used for any application. The new Xilinx App Note XAPP1260, “eFUSE Programming on a Device Programmer,” explains the files you’ll need to program these eFUSE bits and how to use the Xilinx Vivado Design Suite to create an encrypted programming bitstream for use in a device programmer. A link to a reference design is provided as well.

Thanks for that information.
I did not see that the “go to view link” could change documents. I thought it was only within a document.
I manually added two “go to view links” and that seems to work on both mac and pc computers.
That brings up two questions.
For old files can a acrobat java script batch file be setup to read the hyperlinks in a pdf document and replace them with a “go to view link” style?
Can one place a “go to view link” style in a word document and then have the adobe convert to acrobat process it into the pdf format with the rest of the document? (or set up the converter to make word hyperlinks change to pdf “go to view links”?

How to use LabVIEW FPGA on Custom FPGA board other than NI products .....Also how to develop RTx DLL for a customised motion controller hardware

I'm using RTx, LabVIEW RT and LabVIEW FPGA.
The GUI is windows based. The motion control and FPGA are RTx based.
Is there any way to develop device drivers for the custom hardware in RTx. For example motion controller hardware, FPGA hardware, PCI hardware.
Is there a possibility to use custom FPGA boards to use with LabVIEW FPGA.
Please send me some links
Thanks
Bhoopathy
Take life as it comes! you may never know what's gonna happen Tommorrow

CODE WARRIOR Hello. I believe this question was answered in a previous post. Please let us know if you have any new questioins or if you need some clarification.
You are able to develop device drivers for your custom hardware using the NI Measurement Hardware Driver Development Kit.
However, it is not possible to use custom FPGA boards with LabVIEW FPGA. The FPGA boards have to be one of our R Series boards. Here are some links that should shed some light on the Measurement Hardware DDK.
Measurement Hardware Driver Development Kit Frequently Asked Questions
NI Measurement Hardware DDK (Driver Development Kit)
Please post if you have further questios.
Efosa O.
NIAE

Labview FPGA compile stuck at "Place and Routing"

I am using LabVIEW 2010 SP1 32-bit FPGA module. I've built a very large program that was first done back using LabVIEW 8.6, so I have several years experience on LabVIEW FPGA.
When I say it's a large program, I mean that a several times over the last couple years I've tried to add more functionality that has failed to compile do to not enough space on the target or timing restraints. My target has mostly been the PCI/PXI NI-7813R. Due to the nature of our product, a lot has to be done on one FPGA board.
When I do go "over the limit" the compile (after a couple hours) fails and tells me that there's just not enough room on the 7813.
Recently, however, I added some more code, thinking the odds were good that it might push me over the edge. However, the compile never fails. Unfortunately, it never stops either. It gets to the "Placing and routing" portion of the compile and just stays there. When I say stays there, I mean I've run it over night, and when I check it the next morning, the "Elapsed time" is over 10 hours, and still counting up. The device utilization and estimated timing numbers are all under max. And I see no errors in the report so far that I'm used to seeing. Like I said, it just keeps compiling.
I've attached the Xilinx log. It looks much like the log before I added the extra code, except it just stops logging with reporting any useful error.
Anyone have an idea what I could be doing wrong?
Thanks,
Rick
Attachments:
XilinxLog.txt ‏3936 KB

tannerite,
Thanks for your response.
I added code that measures the "on time" of incoming DIO pulses. If the pulses are HIGH for one given amount of time (eg. 60[+/- 5] usecs) it means one thing, if HIGH for a different amount of time (eg. 120[+/- 5] usecs) it means something else. Generally speaking, I just keep a tick count between the rising and falling edge of the pulse, and use the "In Range and Coerce" from the Comparison Functions palette to check where the count lies.
When it compiled successfully, I duplicated the above code for 10 seperate DIOs. Then I realized I needed to monitor 20 DIOs. It was when I added the code for these extra 10 DIOs that I got the "forever" compile. The compile problem occurs everytime I try to compile with the extra 10 DIO code in place. As an experiment, I just added 4 extra DIOs, i.e. code to monitor a total of 14 DIOs. This causes the same compile problem.
And yes, the compile seems to hang in the same place every time it hangs. Like I said, I wouldn't be surprised if I'm just beyond the available resources available. But when I've done this in the past, the compile does finally fail, and I get a useful error message. I've never seen it go "forever".
Thanks ahead of time for any insight you might have.
- Rick

FPGA Compilation fails with Xilinx "Block Memory Generator 8.1" configured with a Coefficient File

Hello All,
I have a SubVI that uses block memory, which has been created using Xilinx "Block Memory Generator 8.1". I have configured this block memory to be a "Single Port ROM", and I use a coefficient file to initialize the memory contents. In simulation mode, everything works as it should.
Next, when I try to compile the top-level VI, I get the following error:
http://www.cs.nyu.edu/~aditya/Compilation_Log_100.txt
http://www.cs.nyu.edu/~aditya/Dividing (This is the coefficient file)
Essentially, the compiler is looking at an ill-formed path to find the coefficient file.
My environment:
-- LabView 2014 f1 (32 Bit)
-- FPGA module 2014
-- RT Module 2014
-- Xilinx Vivado 2013.4
-- NI RIO Drivers 14
-- Development Machine and Conpile Server: Windows 7 Professional, 32GB RAM
-- Compile Worker running Linux, with Xilinx Compile tools installed
Is this a bug, or am I doing something wrong? Thanks!
Best,
Aditya

Next, I tried compiling on the windows machine itself. And here is the error that I get. (See attached image).
Thanks!
best,
aditya
Attachments:
Capture.PNG ‏18 KB

Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
·         The Code size and speed optimization.
·         Developing time.
·         Compiling time.
·         Verifying time.
·         Ability to developing in future.
·         …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
Go to Solution.

Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

How to configure the GPIB controller in LABVIEW or MAX to send UNLISTEN and UNTALK when each message ends?

In a PC to PC GPIB configuration, one PC is used as a non-controller and it reads either LACS or TACS status bits continuously. It apears that the controller PC does not send UNTALK and UNLISTEN at the end of each message. The non-controller reads and writes therefor times-out.
What is the correct message synchronisation for a non-controller?
I use Labview 6, PCIIA, WIN98SE.
Thanks.

Are you using LabVIEW as the controller, non-controller, or both?
NI-488.2 does have a configuration option to enable unaddressing. I am not sure of where it is in LabVIEW, but if you search for unaddressing, you should find some information on it. With unaddressing, NI-488. will unaddress the device after communicating with it.
If you are not using LabVIEW as the non-controller, National Instruments does have a software package called NI-Device that may help. This is an API designed for non-controllers. It does not currently have a LabVIEW interface. It works under C++ with a PCI-GPIB board.
A third option is to rewrite your device application. Your device should really not care about TACS or LACS as you read them from the status register Your device
should only look for LACS, DCAS, and perhaps DTAS (if you desire triggering). When it is LACS, it should read data. After a read has completed, it should interpret the data and get ready for a response. It is only at that moment that the device should look for TACS (and DCAS). It is hard to put a flowchart here, but if you design the flow of a standard instrument, you will see some patterns about when to look for certain status bits.

UDEV rules for Xilinx FPGA devices

I recently purchased a Digilent Nexys3 FPGA board with a Xilinx Spartan 5 FPGA on it. I finally got around to finding some time to using it, and setting up the development environment under Arch linux.
After spending ages reading around about various problems and workarounds, I finally managed to get Xilinx ISE Webpack installed and working, as well as Digilent Adept software for downloading the designs to the development board. One issue still remains though. I am unable to download the designs to the FPGA as a normal user, but only as root.
I'm pretty sure this is a udev rules problem. Digilent supplies a rules file (attached below) which is supposed to grant permissions to all users to access the FPGA devices over USB. I placed this rule file under /etc/udev/rules.d, but I am still unable to access the devices as normal user due to the following error:
$ djtgcfg enum
libusb couldn't open USB device /dev/bus/usb/001/003: Permission Denied.
libusb requires write access to USB device nodes.
$
I believe that udev rules syntax changed since the last time I had a look at it, so maybe the supplied rules file still uses the old syntax? Any suggestions to fixing this rules file (attached below)?
# 52-digilent-usb.rules -- UDEV rules for Digilent USB Devices #
# Author: MTA #
# Copyright 2010 Digilent Inc. #
# File Description: #
# This file contains the rules used by UDEV when creating entries for #
# Digilent USB devices. In order for Digilent's shared libraries and #
# applications to access these devices without root privalages it is #
# necessary for UDEV to create entries for which all users have read #
# and write permission. #
# Usage: #
# Copy this file to "/etc/udev/rules.d/" and execute #
# "/sbin/udevcontrol reload_rules" as root. This only needs to be done #
# immediately after installation. Each time you reboot your system the #
# rules are automatically loaded by UDEV. #
# Revision History: #
# 04/15/2010(MTA): created #
# 02/28/2011(MTA): modified to support FTDI based devices #
# Create "/dev" entries for Digilent device's with read and write
# permission granted to all users.
SYSFS{idVendor}=="1443", MODE="666"
ACTION=="add", SYSFS{idVendor}=="0403", SYSFS{manufacturer}=="Digilent", MODE="666", RUN+="/usr/local/sbin/dftdrvdtch %s{busnum} %s{devnum}"
# The following rules (if present) cause UDEV to ignore all UEVENTS for
# which the subsystem is "usb_endpoint" and the action is "add" or
# "remove". These rules are necessary to work around what appears to be a
# bug in the Kernel used by Red Hat Enterprise Linux 5/CentOS 5. The Kernel
# sends UEVENTS to remove and then add entries for the endpoints of a USB
# device in "/dev" each time a process releases an interface. This occurs
# each time a data transaction occurs. When an FPGA is configured or flash
# device is written a large number of transactions take place. If the
# following lines are commented out then UDEV will be overloaded for a long
# period of time while it tries to process the massive number of UEVENTS it
# receives from the kernel. Please note that this work around only applies
# to systems running RHEL5 or CentOS 5 and as a result the rules will only
# be present on those systems.
Thanks!
-Igor
Last edited by UQ-igor (2011-12-24 03:56:10)

Try this
Use ATTR or ATTRS.
-SYSFS{idVendor}=="1443", MODE="666"
-ACTION=="add", SYSFS{idVendor}=="0403", SYSFS{manufacturer}=="Digilent", MODE="666", RUN+="/usr/sbin/dftdrvdtch %s{busnum} %s{devnum}"
+ATTRS{idVendor}=="1443", MODE="666"
+ACTION=="add", ATTRS{idVendor}=="0403", ATTRS{manufacturer}=="Digilent", MODE="666", RUN+="/usr/sbin/dftdrvdtch %s{busnum} %s{devnum}"
+ATTR{idVendor}=="1443", MODE="666"
+ACTION=="add", ATTR{idVendor}=="0403", ATTR{manufacturer}=="Digilent", MODE="666", RUN+="/usr/sbin/dftdrvdtch %s{busnum} %s{devnum}"

How to generate 8.192MHz clock on labview FPGA 7854R series card?

Hi,
I am using NI PXI-7854R series card which has Xilinx Vertex 5 FPGA on it. I am trying to derive a clock of 8.192 MHz from the 40MHz on board clock of FPGA. But it ends up giving me only 8MHz clock. Is there any way of accessing the PLL which is on Xilinx FPGA?
Regards
Solved!
Go to Solution.

If you are familliar with VHDL you can make your own "Component Level IP" (aka CLIP) with a Xilinx PLL inside. There are topics in the help and examples showing how to define a CLIP. Here is one that shows how to instantiate a DCM (similar to a PLL) in a CLIP:
http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgahelp/fpga_clip_clock_ex_code/

How to create a virtual FPGA and run LabVIEW code on it?

Hi
I am new to LabVIEW FPGA world. I have code written in LV 8.6 that was running on a Virtex 5. I need to run this code on a virtual FPGA but I need this to be as real as possible and maybe to acces this virtual FPGA also from another environment. Do you think this can be done? I need just a general answer to have an idea on this problem.
Thanks

If I've understood correctly, you have LabVIEW code written for an FPGA and running on an NI FPGA board, which you'd now like to run in a simulated system. I doubt this is possible since I don't think there is a way for you to simulate all the hardware (DAQ and whatever else) that is attached to the FPGA on the real hardware. Also, LabVIEW doesn't have any way of accessing an arbitrary non-NI FPGA target and without the LabVIEW interface I don't think your FPGA code will be too useful.

Labview vs Xilinx controller on FPGA

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