MIG v2.3 clock skew

Question

Hi,
I am having issues closing timing on a design that uses the MIG to interface (via AXI4) to DDR3 (AXI clock = 250MHz, DDR3 clock = 500MHz). In the failing paths (-200ish ps WNS) the problem appears to be down to clock skew between the source and destination clocks on the AXI4 read interface (see report snippet below).
I think this is down to the fact that I am not using the user clock output from the MIG, but the original system clock to register the read data.
Is it possible to effectively de-skew the two clocks?
Regards
Max Delay Paths
Slack (VIOLATED) :        -0.226ns  (required time - arrival time)
Source:                 i_playout_block_wrapper/mig_7series_0_i/u_mig_7series_0_mig/u_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[19].FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by clk_pll_i  {[email protected] [email protected] period=4.000ns})
Destination:            i_playout_block_wrapper/playout_block_i/axi4_register_slice_64_wrapper_mem_read_arbiter/axi4_register_slice_64_i/inst/r_pipe/skid_buffer_reg[46]/D
                            (rising edge-triggered cell FDRE clocked by clkout0  {[email protected] [email protected] period=4.000ns})
Path Group:             clkout0
Path Type:              Setup (Max at Slow Process Corner)
Requirement:            4.000ns  (clkout0 [email protected] - clk_pll_i [email protected])
Data Path Delay:        1.673ns  (logic 0.309ns (18.471%)  route 1.364ns (81.529%))
Logic Levels:           2  (LUT5=1 LUT6=1)
Clock Path Skew:        -2.342ns (DCD - SCD + CPR)
Destination Clock Delay (DCD):    7.241ns = ( 11.241 - 4.000 )
Source Clock Delay      (SCD):    10.889ns
Clock Pessimism Removal (CPR):    1.306ns
Clock Uncertainty:      0.192ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter     (TSJ):    0.071ns
Discrete Jitter          (DJ):    0.104ns
Phase Error              (PE):    0.130ns
Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)

Answer 1

Hi
answer q1
This error because your second node time was greater than node one, this is causing OUI failed in running tar command on second node.
you need to set node 2 time slighter less or equal to node 1 time
answer q2
yes we can proceed installation with package greater or equal than required
answer q3
it seems your VMs memory allocation were to small (512MB). I don't think that would be enough to installing rac.
and try to install required packages
Cheers
FZheng