Modem Pass through to remote PBX
Dear All,
I would like to use the cisco router 3640 (with T1 card) and cisco 2621 (with 2 x FXS card) to simulate the network & pstn environment to test the modem pass through, here is the detail connection:
Analog Phone (Ext: 451660) <--> [FXS] Cisco Router 2621 <---- LAN ----> Router 3640 [T1] <--> [T1] PBX (Panasonic) <--> Analog Phone (Ext: 454820, Modem)
The dial-peer on the router 2621 & 3640 is working as I can call in/out from PBX analog phone, and I was success to connect the PC (with modem port, and use the hyperterminal, atdt454820) from Outside PC (with modem port, Ext: 451660).
But I was fail to dial-out from PBX analog phone (454820) to 451660.
From Cisco router 2600:
dial-peer voice 45166 voip
destination-pattern 45166.
modem passthrough nse codec g711ulaw redundancy
session target ipv4:192.168.0.60 (Router 3640)
From Cisco router 3640
dial-peer voice 454820 voip
destination-pattern 454820
modem passthrough nse codec g711ulaw redundancy
session target ipv4:192.168.0.44 (Router 2600)
Here is the link I try to follow to do:
http://www.cisco.com/en/US/docs/ios/12_1t/12_1t3/feature/guide/dtmodptr.html
I would like to know if there is any miss-configure or how can I troubleshoot (to find out the cause) which I cannot connect from PBX' PC.
Thanks!
Note that anytime a call traverses a voice gateway, we match *two* dial-peers, not one. We match one inbound, and one outbound. In your scenario, if the FXS side originates the call, it would be:
fxs(inbound pots)router(outbound voip)----LAN-----(inbound voip)router(outbound pots)---T1
The algorithm for how this works is documented in this link. I recommend having a few reads over this:
http://www.cisco.com/en/US/tech/tk652/tk90/technologies_tech_note09186a008010fed1.shtml
If you can get these debugs, I can take a deeper look into the failure:
debug voip ccapi inout
debug isdn q931
debug vpm sig
debug h225 asn1
debug h245 asn1
Collect these in the following manner:
Router(config)# service sequence
Router(config)# service timestamps debug datetime msec
Router(config)# logging buffered 10000000 7
Router(config)# no logging con
Router(config)# no logging mon
Router(config)# voice iec syslog
Router# term len 0
Router# sh logg
Also send the full configs of both gateways.
-Steve
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crypto ipsec transform-set aes-256-sha esp-aes-256 esp-sha-hmac
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crypto isakmp policy 12
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[URL=http://minus.com/liKoug8pFOaFN][IMG]http://i.minus.com/jiKoug8pFOaFN.jpg[/IMG][/URL]
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Q. Can I install an access point (AP) at a remote office and install a Cisco WLC at my headquarters? Does the Lightweight AP Protocol (LWAPP) work over a WAN?
A. Yes, you can have the WLCs across the WAN from the APs. LWAPP works over a WAN. Use Remote Edge AP (REAP) mode. REAP allows the control of an AP by a remote controller that is connected via a WAN link. Traffic is bridged onto the LAN link locally, which avoids the need to unnecessarily send local traffic over the WAN link. This is precisely one of the greatest advantages of having WLCs in your wireless network.
Note: Not all lightweight APs support REAP. For example, the 1030 AP supports REAP, but the 1010 and 1020 AP do not support REAP. Before you plan to implement REAP, check to determine if the APs support it. Cisco IOS Software APs that have been converted to LWAPP do not support REAP.
Q. I want to set up the Cisco 1030 Lightweight Access Point (AP) with a Cisco WLC in Remote Edge AP (REAP) mode. In this mode, is all wireless traffic tunneled back to the WLC? Additionally, if the AP cannot contact the WLC, what happens to the wireless clients?
A. The 1030 AP tunnels all WLC traffic (control and management traffic) to the WLC via Lightweight AP Protocol (LWAPP). All data traffic stays local to the AP. The 1030 REAP can only reside on a single subnet because it cannot perform IEEE 802.1Q VLAN tagging. As such, traffic on each service set identifier (SSID) terminates on the same subnet on the wired network. So, while wireless traffic may be segmented over the air between SSIDs, user traffic is not separated on the wired side. Access to local network resources is maintained throughout WAN outages.
At times of WAN link outage, all WLANs except the first is decommissioned. Therefore, use WLAN 1 as the primary WLAN and plan security policies accordingly. Cisco recommends that you use a local authentication/encryption method, such as the Wi-Fi Protected Access (WPA) Pre-Shared Key (WPA-PSK), on this first WLAN.
Note: Wired Equivalent Privacy (WEP) suffices, but this method is not recommended because of known security vulnerabilities.
If you use WPA-PSK (or WEP), properly configured users are still able to gain access to local network resources even when the WAN link is down.
From this doc;
http://www.cisco.com/en/US/products/ps6366/products_qanda_item09186a008064a991.shtml
Hope this helps!
Rob
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CUCM ISUP-OLI / ANI II pass-through
Hi, I've a Cisco UBE that receive a SIP calls from a remote provider. This provider send ANI-II Digits into a From header like:
Received:
INVITE sip:[email protected]:5060 SIP/2.0
From: <sip:[email protected]:5060>;isup-oli=00;tag=SDs1ts901-10.50.83.40+1+161e1d+61e8c298
but when CUBE pass-through this call it strip ANI II Digits
Sent:
INVITE sip:[email protected]:5060 SIP/2.0
From: <sip:[email protected]>;tag=850A3664-1051
Is there any way to avoid this? I need to pass-through ISUP-OLI on From header.I found this document that describe what I need.
http://www.cisco.com/c/en/us/td/docs/ios-xml/ios/voice/cube/configuration/cube-book/pass-unsupported.html -
Data has changed after passing through FIFO?
Dear experts,
I am currently working on a digital triangular shaping using the 7966R FPGA + 5734 AI. I am using LabView 2012 SP1.
Some days ago I have encountered a problem with my FIFOs that I have not been able to solve since. I'd be glad if somebody could point out a solution/ my error.
Short description:
I am writing U16 variables between ~32700-32800 to a U16 configured FIFO. The FIFO output does not coincide with the data I have been writing to the FIFO but is rather bit-shifted or something is added. This problem does not occure if I execute the VI on the dev. PC with simulated input.
What I have done so far:
I am reading all 4 channels of the 5734 inside a SCTL. The data is stored in 4 feedback nodes I am applying a triangular shaping to channel 0 and 1 by using 4 FIFOs that have been prefilled with a predefined number of zeros to serve as buffers. So it's something like (FB = Feedback node):
A I/O 1 --> FB --> FIFO 1 --> FB --> FIFO 2 --> FB --> Do something
A I/O 2 --> FB --> FIFO 3 --> FB --> FIFO 4 --> FB --> Do something
This code shows NO weird behaviour and works as expected.
The Problem:
To reduce the amount of FIFOs needed I then decided to interleave the data and to use only 2 FIFOs instead of 4. You can see the code in the attachment. As you can see I have not really changed anything to the code structure in general.
The input to the FIFO is a U16. All FIFOs are configured to store U16 data.
The data that I am writing to the FIFO can be seen in channel 0 of the output attachment.
The output after passing through the two FIFOs can be seen in channel 2 of the same picture.
The output after passing through the first FIFO (times 2) can be seen in channel 3 of the picture.
It looks like the output is bit-shifted and truncated as it enters Buffer 1. Yet the difference between the input and output is not exactly a factor of 2. I also considered the possibility that the FIFO adds both write operations (CH0 + CH1) but that also does not account for the value of the output.
The FIFOs are all operating normally, i.e. none throws a timeout. I also tried several different orders of reading/writing to the FIFOs and different ways of ensuring this order (i.e. case strucutres, flat and stacked sequence). The FIFOs are also large enough to store the amount of data buffered no matter if I write or read first.
Thank you very much,
Bjorn
Attachments:
FPGA-code.png 61 KB
FPGA-output.png 45 KBDuring the last couple of days I tried the following:
1. Running the FPGA code on the development PC with simulated I/O. The behavior was normal, i.e. like I've intended the code to perform.
2. I tested the code on the development PC with the square and sine wave generation VI as 'simulated' I/O. The code performed normal.
3. I replaced the FIFOs with queues and ran my logic on the dev. PC. The logic performed totally normal.
4. Right now the code is compiling with constants as inputs like you suggested...
I am currently trying to get LabView 2013 on the development machine. It seems like my last real hope is that the issue is a bug in the XILINX 13.4 compiler tools and that the 14.4 tools will just make it disappear...
Nevertheless I am still open for suggestions. Some additional info about my FIFOs of concerne:
Buffer 1 and 2:
- Type: Target Scoped
- Elements Requested: 1023
- Implementation: Block Memory
- Control Logic: Target Optimal
- Data Type: U16
- Arbitrate for Read: Never Arbitrate
- No. Elements Per Read: 1
- Arbitrate for Write: Never Arbitrate
- No. Elements Per Write: 1
The inputs from the NI 5734 are U16 so I am wirering the right data type to the FIFOs. I also don't have any coercion dots within my FPGA VI. And so far it has only occured after the VI has been compiled onto the FPGA. Could some of the FIFOs/block memory be corrupted because we have written stuff onto the FPGA too often?
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