Multiple pulse trains

I have to figure out a LabView program written by someone, which was basically used to generate 2 pulse trains alternating (ABABAB....). I need to modify the program so I can generate 3 alternating pulse trains (ABCABCABC....) using 3 counters (PXI 6602 and traditional DAQ).
A       ------------                                  ------------                                  ------------
         |              |                                 |               |                                |              |
         |              |                                 |               |                                |              |
B                      -------------                                   --------------
                        |                 |                                 |                 |
                        |                 |                                |                 |
C                                       ------------                                       ------------
                                        |               |                                      |              |
                                       |               |                                     |              |
When I looked at a typical Pulse Train Generation TIO. vi given below, I saw the pulse spec 1 (for idle time) and pulse spec 2 (for pulse length).
Is it possible to put another counter set attribute with pulse spec 1 after the pulse spec 1 and 2 again in order to give more delay time?
This will help a lot for me to modify the existing program in order to generate the 3 alternating pulse trains.
pchemjjang
Attachments:
Pulse Train Generation TIO test.vi ‏77 KB

Hi pchemjjang:
For a pulse train generation set up you will use one counter per pulse. In your case you card have 8 counters so you should be able to add another counter and change the delays to generate pulse phase delayed 180 degrees one from the other one, I have not tried it here so I’m not sure what obstacles you may find trying to setup this task. Here is an example that basically does the same but with four counters.
I know you are adding functionality to a program already written in Traditional DAQ, but you may consider NI-DAQmx for this or future development. This is especially important if you happen to upgrade your system in the future as any current and future hardware releases by NI will only be supported by the NI-DAQmx driver. Here’s a good link to get you started: Getting Started with NI-DAQmx: Main Page. I would also suggest reading: Transition from Traditional NI-DAQ to NI-DAQmx in LabVIEW, and the best thing you can look at is this examples code and these tutorials in traditional DAQ.
Jaime Hoffiz
National Instruments
Product Expert
Digital Multimeters and LCR Meters

Similar Messages

Generating multiple Pulse Trains.

I am trying to generate two different pulse trains. Once the first pulse train has begun I need to start the
second pulse train approximately .69444 ms after the first has started. I am currently using the two counter channels on the NI ELVIS, but the second pulse doesn't always start after the first, but it does work sometimes. How can I fix this? Attached is my vi file.
Thanks,
David
Note: Each pulse train has a 33% duty cycle.
Attachments:
SaO2.vi ‏91 KB

Hello,
Here is what I would try:
1. Set up counter 0 to perform a continuous pulse train (see the LabVIEW example called Gen Dig Pulse Train-Continuous.vi)
2. Set up counter 1 to perform a continuous pulse train with a digital start (see the LabVIEW example Gen Dig Pulse Train-Continuous-Dig Start.vi)
A. Modify this example code so that the trigger source is your counter 0 output.
B. Modify this example code so that the initial delay value of the pulse train is 0.7 milliseconds (or whatever delay you want). Create the delay with the input to the DAQmx Create Channel VI (the delay is currently set with a default of 0.00 seconds).
What you are doing is triggering the second counter off of the rising edge of the first counter. So, counter 0 will start generating a pulse train. Counter 1 will not start until the rising edge of counter 0's first pulse has occurred. Once this trigger has occurred, Counter 1 will start (after the initial delay time of 0.7 ms has passed). You can cut and paste to put the code of the two examples together.
Hope this works for you,
Sam

How can I generate synchronized pulse trains with 6602?

Hi,
I would like to generate multiple pulse trains with different frequencies with the 6602 TIO card. Currently I am able to generate pulse trains with different frequencies. But is there any way to synchronize all the pulse trains? For example, I'd like to have all pulse trains with their first low-to-high at the same moment.
Thanks!
Dan

Dan,
Absolutely, the NI-TIO chip on the PCI-6602 supports a start trigger. If you configure all of the counters that are generating a pulse train to use this start trigger, they will be synchronized. The example Generate Pulse Train - Start Trig (NI-TIO).vi demonstrates this process for one counter. In LabVIEW 7, this example can be found in the following location:
Examples >> Hardware Input and Output >> Traditional DAQ >> Counters >> NI-TIO
You will need to add code for the other counters, but this example should give you the general idea. Furthermore, this example demonstrates how you can use one of the digital lines to generate the start trigger.
Good luck with your application.
Spencer S.

How do I output a finite pulse train through multiple counters?

Hello,
I have used LabView examples to create a VI to use with my TIO 6602 that generates a finite pulse train with varying duty cycle, frequency, number of pulse, and initial delay. I can also have it output the pulses through multiple counter channels, but all the channels have the same delay, and are output at the same time. I need each channel to have a specific delay from the first one.
In my VI, I use DAQmx to create a retriggerable finite pulse train by gating a counter with another counter. I have all the neccessary controls over the pulse train, but I can not seem to find an easy way to just copy this waveform and output delayed versions of it to other channels. The delay is very important because these signals will be used to drive ultrasound transducers in a linear array, and for the waveforms to focus at one point, the signal driving the transducers with a shorter distance from the focal point need a larger delay, so that the same waveform arrives from each transducer at the same time.
Any help with how I might do this would be much appreciated.
Thanks!

Hey Sneaky,
Here's a screenshot of the code I put together on how to use multiple counters. Also, take a look here for more information on how to sync multiple counters.
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:38 AM
-John Sullivan
Analog Engineer
Attachments:
4xcount.jpg ‏67 KB

Pulse train generation fails with certain values for "number of samples"

I'm generating a retriggerable analog output signal, and so I'm using a counter as the sample clock (see: Retriggerable AI Using Retriggerable Counter). I am finding that, above a certain number of samples, and only for certain values of the number of samples, the counter task gives me error -200305, "Desired finite pulse train generation is not possibe." The error crops up only when actually starting the task.
The analog signal that I'm trying to generate will be about 800 kHz, so my counter is set to run at the same frequency. I find that the counter task works fine if the number of samples to generate is anywhere between zero and 671,088 samples. Setting the number of samples to 671,089 gives the error above, as does 671,090 samples and so on. However, using 671,096, the counter task works fine. After that, the counter seems to output fine only if the number of samples is divisible by 8.
The only thing I can think of is that (617088 samples) / (800000 Hz) = 0.839 s. At the internal clock rate of 20 MHz, 0.839 s is 2^24 samples, and it is a 24-bit counter on this hardware. So if it's this internal counter rolling over, that's fine and I can work around that. But if that's the case, what I don't understand is why increasing the number of samples in increments of 8 samples still works.
The hardware is a PXI-6733 board, running with LabView 7.1.1 and NI-DAQmx 8.1.

Hmmm, multiples of 50 & 100? Now I'm puzzled again.
Here's how to make sense of the 100 kHz timebase idea though, even if it turns out not to be the right explanation. For a retriggerable finite pulse train, you actually use a pair of counters. If you were to program it manually, you could set your output counter to generate a continuous pulsetrain at 800 kHz using the internal 20 MHz timebase. This output counter would also be configured to use the other counter's output as a digital level-based pause trigger. So the 800 kHz pulsetrain is only output while the other counter's output is, say, high.
The other counter is configured for retriggerable pulse generation. The pulse duration or high time should be set for (# pulses) / (800e3 pulses/sec). This other counter can be configured to use the 100 kHz timebase, so its high time would then have to be an integer multiple of 10 usec.
So let's see... An 800 kHz pulsetrain is possible with a 20 MHz timebase (exactly 25 cycles). A 700 kHz (28 + 4/7 cycles) or 900 kHz (22 + 2/9 cycles) is not. So when you request those other frequencies, you actually get a near approximation. I dunno if DAQmx can be queried for the actual value correctly or not -- I recall an early version that reported back whatever freq you had asked for rather than what it actually used. Queries based on ticks (rather than time or freq) did return what was actually used, as I recall.
Let's suppose a request for 700 kHz gets truncated to 28 cycles of the 20 MHz timebase making a 1.4 usec period. Then 50 of those periods becomes 70 usec, which is evenly divisible by the 100 kHz timebase. Bingo! (Note: 70 is the least common multiple of 10 and 1.4)
Now suppose the request for 900 kHz turns into 22 cycles of the 20 MHz timebase, or a 1.1 usec period. Now it takes 100 of those periods to get to 110 usec, which is also evenly divisible by the 100 kHz timebase. Bingo again! (Note: 110 is the lcm of 10 and 1.1).
Did you follow the method here? It should help you figure out expected results for various output freqs and #'s of samples.
-Kevin P.

Can I generate pulse trains on more than one counter output at the same time?

I have a PCI 6601 card with a BNC 2121 to connect the signals to two devices. The card is used as a trigger for both devices and I want to be able to generate pulse trains on two output channels at the same time, with a time delay between the two. How do I do that in Labview 7.1 Development with DAQmx?

I feel foolish for not being able to figure this out, but it still doesn't work. Attached is the VI I use now. Counter 0 generates a finite pulse train and I programmed Counter 1 to generate a retriggerable single pulse triggered by CtrOinternaloutput. I still get the same error message: -50103 The specified resource is reserved. The operation could not be completed as specified.
The same happens if I set the trigger for counter 1 at PFI36 (default output of counter 0) or any other PFI line. If I try a pulse train generation on only one of the counters, both work fine.
If I try the example in traditional DAQ for multiple counter outputs with phase delay, it works fine.
Can you tell me what I'm doing wrong?
Attachments:
Shutter_AND_lamp_trigger.vi ‏103 KB

How to generate sequence of pulse trains with DAQmx?

I need to generate a sequence of pulse trains with DAQmx (the card I have is a PXI-6229 card). As an example:
- 10'000 pulses at 20kHz every 5 seconds with an initial offset of 2 seconds (let's say 10 pulse trains in total).
If I use the CreateVirtualChannel.vi in "CO pulse ticks" mode, I can only specificy offset, high ticks and low ticks, but not that the sequence of pulses should be repeated after some time.
Now I thought that I could solve this problem if it were possible to multiply two counter outputs: the first counter would generate the pulses (continuously) whereas the second one would switch between low and high on a slower timescale in order to gate the first counter, thereby providing an initial offset and the "off" phases between the pulse trains.
Is it somehow possible to multiply two outputs with DAQmx and the card I have? Or is there another solution to the problem?
Thanks a lot in advance for any hints!

Hi dlanger,
what you want to do requires a little bit more work.
First look at the example "Gen Dig Pulse Train-Continuous.vi" from the LV example finder.
This example generates a continuous* pulse train. As you see, you need a sample clock VI for setting the sample mode.
* NOTE: Generating a finite pulse train with a M-series card requires 2 counter.
With a pause trigger (DAQmx trigger property node) you can gate the output of that counter.
Now you have to generate a gate-signal with the the 2nd counter. That means, only if Ctr1-out is high Ctr0-out outputs the 20 kHz-signal.
Maybe you have to adjust the times in my example a bit.
Unfortunately there is just one "small" problem: "let's say 10 pulse trains in total"
This is not possible, because a 3rd counter would be necessary (*).
As a workaround you can modify the while-loop that both tasks are cleared after 50s. This is not brilliant, but should work fine for you.
A more sophisticated way is to perform a correlated DIO. So you can generate custom pattern for multiple outputs.
A good example can you find here:
Retrigger and Repeat Finite Digital Pulse Train in LabVIEW
http://decibel.ni.com/content/docs/DOC-8473
or here:
Generating More Than 2 Pulse Trains Using CompactDAQ
http://decibel.ni.com/content/docs/DOC-2167
Hope this helps.
With best wishes,
Ralf N.
Attachments:
Gen Gated Dig Pulse Train-Continuous.vi ‏38 KB

Retriggerable finite pulse train

I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continueous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on between pulse trains, when it should be turned off. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. I use the ActualPeriod of the first re-triggerable pulse to ensure the pulse train ends correctly within window of the first re-triggerable pulse, but it seem to wander. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem. I may have to use a single re-triggerable pulse instead of a re-triggerable pulse train as this work correctly every time. However, multiple pulses creates a finer mist from a fuel injector and is the correct why to modulate a fuel injector. The

CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

Pulse train generation - questions about PLL and jitter

I need to generate a pulse train having a pulse width of 20ns and a period up to 100ms, selectable by software.
The jitter requirement of the period is 10ppm (1us over 100ms).
I thought to use PCI6221 to generate this pulse train but I could not find all answers in its documentation or anywhere else.
1. Can the PLL be used to get a clock frequency to the counters of 50MHz out of the internal clock of 80MHz (5/8 factor)?
2. Can the counters be set to output a pulse width of a single clock period in "Pulse Train" mode? (then the above 50MHz clock gives the 20ns pulse width).
3. The datasheet states the base clock accuracy is 50 ppm, in "Frequency Generator" mode. What is the clock period jitter in "Pulse Train" mode, including the PLL effect?
Is there any other counter/timer board that may be better for this job?
Thanks.

For this task first let’s take a look at the counter
specification of the 6221.
3. The datasheet states the base clock accuracy is 50 ppm,
in "Frequency Generator" mode. What is the clock period jitter in
"Pulse Train" mode, including the PLL effect? NI 622x Specifications
page 9 states as you said 50 ppm for the “Frequency Generator” for the pulse
train mode it will be the same 50 ppm as it is stated I below the: “General-Purpose
Counter/Timers” title.
I hope this knowledge base helps: How
Do I Change The Frequency Output Of My Pulse Train On The Fly?
You will not be able to generate a 20 ns
pulse, since you can only derive integer multiples of the 80 MHz time base in
this case, 1/40MHz pulses will be the closest you can get to a 20 ns
pulse. Also another note is that the
frequency generator does not have a selectable pulse width, it is a 50% duty
cycle signal.
For more information look at the M Series User Manual page 7-21.
Two other products that you might be
looking at are High Speed Digital Inputs and Outputs and Function Generators;
take a look at those and post on the right discussion forum if you have any
questions.
Message Edited by Jaime F on 05-05-2008 05:38 PM
Jaime Hoffiz
National Instruments
Product Expert
Digital Multimeters and LCR Meters

Retriggerable gated counter or analog pulse trains

Hi all,
I have a problem I could not resolve in the last days. It might be even a question of creativity of how to come up with a solution.
I have an external pulse train 1 at ca. 8 kHz (frequency not fully stable). With this pulse train, I want to trigger with each pulse an analog waveform. Using X-series boards, this works perfectly.
But now I want to gate this analog signal with another pulse train 2 that is much slower than the other one (pausetrig option). Theoretically, this works nicely, too. But in reality, the analog signal simply ends at the point where it is stopped by the pause trigger, whereas I want it to stop at the end point of the waveform.
Please have a look at the drawing attached
I would be really glad about any ideas on how to solve this problem.
Best regards,
Peter

I don't think I've ever defined both a start trigger and a pause trigger defined for the same task. Good to know it's allowed.
Given what you've already found, the solution is to control the timing of the end of the pause trigger pulse's active state (shown here as high).
Here's one approach:
1. Create the pause trigger pulse with a retriggerable single pulse task. Use a minimal "low time" and "initial delay". Set the high (active) time to be approximately (N+1) periods of your AO sample clock.  Technically, N+1 periods is a bit more than necessary, but it's sure to be enough and doesn't require research into deep details of AO timing.
2. Configure the AO task to use the pulse as *both* its start trigger (rising edge) and its pause trigger (pause when low).
Comments: this makes for a different timing diagram than you've drawn. Each external 8 kHz pulse causes a minimally-delayed pause trigger pulse which lasts long enough to generate the full AO waveform but ends before the next 8 kHz pulse. The choice of when to start and stop this trigger pulse will be up to your own logic and will be governed by software timing.
   Oh dang! That still leaves you susceptible to a partial waveform since you can't sync the software timing to occur during the desired small fraction of the 8 kHz interval with no AO waveform.
Second approach:
1. Similar to #1 above, but set the high (active) time to cover multiple 8 kHz periods and *don't* make the task retriggerable. To get the timing right in hardware, you'll need to generate a pulse that's *approximately* the requested length, but you'll reserve the right to tweak it so the edges fall in the right place.   You'll also define your pulse in terms of the external 8 kHz signal rather than in terms of internal board time.
     Specifically, configure to generate a pulse based on units of "Ticks" using the rising edges of the external 8 kHz signal as the "source of ticks." Set a minimal value (probably 2) for both the "low ticks" and "initial delay" inputs. The "high ticks" setting is where you do your tweaking.
    Suppose the desired pause trigger time is 10.3 msec. Nominally, that's 82.4 intervals of the 8 kHz external signal. Well, just round up or down as you see fit and wire this integer # into the "high ticks" input.
2. AO task is configured to retrigger off the external 8 kHz signal and be pause triggered by #1's counter pulse.
Comments: When you start the pause trigger pulse task, it will remain in its low idle state for the first two 8 kHz pulses. It will go high on the 3rd pulse and then revert low on the 82nd subsequent pulse.
   Because this pulse *also* acts as a pause trigger for the AO task, you're now synced such that the AO task is paused exactly as it is being retriggered, meaning that the previous waveform must have been allowed to complete. (The deep details of timing will prevent the AO task from generating 1 sample at this instant.)
-Kevin P

Generate a pulse train

How do I generate finite pulse train of 3 pulses of 25us pulse width, pulse period (1/(7000Hz)), and retrigger the same finite pulse train every 588.23us with the PCI-6602?
What are the externals connections?
What is the right Labview programming?

this can be done with the 6602 using multiple counters, but this board has 8 so you will still have many left over for other tasks.
You will need essentially 2 tasks, one taks is a retrigerable gated finite pulse train and the other is a simple finite pulse train.
I have done something similar using DaqMX and LV 7.0
To create the finite pulse train, create a CO.PulseTime task, create a channel setting the high times and low times (25 microseconds)and set the low polarity. I will assume that such a pulse train is going to trigger some external event or other DAQ card. Next set the timing to be implicit and sample mode to be finite and the number of pulses to be 3. To handle the retriggering and gate properities use a channel properitiy node and select:
StartTrigType = Digital Edge;
Start.Retrigerable = True;
Start.DigEdge.Edge = Rising;
Start.DigEdge.Src = PFI number of the out from the continious pulse train.
This last option will allow you to route the trigger from the controlling pulse trian to trigger your finite pulde train.
Now set up a second task to put out a continious pulse train with the period equal to the total durration between finite pulse trains (~500microseconds I dont have the exact number in front of me).
After creating these two tasks, start the retriggerable task first.
now when you start the continious pulse train you will get a finite pulse train of 3 pulses every time the rising edge of the continious pulse train fires. Stop and start the continious pulse train using software at will but only stop the finite task when you are done. Hope this helps.
-Paul
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA

Signal generator Pulse train with switch cycle

Bonjour,
J'essaie de générer un signal avec un rapport cyclique tres variable sur une carte PCI6602
Par exemple,
j'utilise en signal source internal clock de 20MHz et je souhaite que mon signal soit de la forme suivante :
4cycles d'horloge à l'etat haut
puis 2cycles d'horloge à l'etat bas
puis 17cycles d'horloge à l'etat haut
puis 4cycles d'horloge à l'etat bas
puis 20cycles d'horloge à l'etat haut
puis 5cycles d'horloge à l'etat bas
pour cela j'utilise le generateur de signaux Pulse Train avec la fonction ND_SWITCH_CYCLE
mais en verifiant à l'oscillo je ne vois pas le signal varier de cette sorte juste appliquer le dernier rapport cyclique défini.

Unfortunately, I don't think you can accomplish that with a 6602. The only way to change the pulse specs on-the-fly is through software calls to the driver, and those won't execute nearly as quickly as you need. You would need to change the pulse specs for each and every pulse, and do it at a rate of ~1+ MHz. The software calls will limit you far below that -- I'd guess somewhere in the order of 10 kHz.
There's a further issue that you must let the prior pulse specs produce a pulse before the new pulse specs are allowed to take their place. So even for very slow pulse trains, it's difficult if not impossible to produce exactly one pulse at each set of specs.
What is needed (see my wishlist starting at reply #10-11) is the ability to perform hw-timed buffered counter pulsetrain outputs. Some of the M-series boards allow for hw-timed digital output at rates up to 10 MHz, but it appears that some of your intervals need to be odd multiples of a 20 MHz clock. Some of the high-speed digital boards could work, but you're looking at ~$2000.
How many cycles of precisely-timed pulses do you need? If 8 or fewer, there may be a way to setup a bunch of separate counters that are hw-triggered to start simultaneously, but each produces a single pulse with just the right specs. Then you'd need an output logic circuit which would essentially OR all the counter outputs together to produce the 1 output you need.
-Kevin P.

How to generate an (re-) synchronized pulse train

Hello,
using a PCI-6601
I want to generate an endless pulse train of (e.g. 80Hz, high==low) synchronized to an external clock (ca.1Hz, ca 5ms pulse width).
The output should _re_synchronize with the clock if there is a clock signal but if one clock-pulse is missing it should continue hoping for the next.
It should look like this:
Perfect:
A1) tt________________tt________________tt_________...
A2) ooo___ooo___ooo___ooo___ooo___ooo___ooo___ooo__...
    0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5_...
Output is too fast:
B1) tt_________________TT________________tt________...
B2) ooo___ooo___ooo___oxxx___xxx___xxx___xxx___xxx_...
    0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5_...
Output is too slow:
C1) tt_______________PP________________tt__________...
C2) ooo___ooo___ooo__xxx___xxx___xxx___xxx___xxx___...
    0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5_...
Clock is missing:
D1) tt________________._________________tt__________...
D2) ooo___ooo___ooo___xxx___xxx___xxx___xxx____xxx__...
    0__1__2__3__4__5__6__7__8__9__0__1__2__3__4__5__...
The external clock is assumed to be "the truth", so the pulse width for the 80Hz output is recomputed from time to time
by measuring the clock and then setting then output pulse width.
Until now I used register programming but this is not a must.
The examples I've found either generate finite pulse trains or the sync only once.
Is there a way to do what I want without software interaction?
Thanks in advance
Toni Schilling

I have a possible idea for you, but my experience is with LabVIEW so I can't offer any help with register programming, interrupt callbacks, etc. Also, the continuous syncing will have to be a software function that continuously performs cycles of measure/adjust, measure/adjust, measure/adjust...   I know of no way to set up the hardware to do this autonomously.
The approach I would take is to add another counter task and a little extra wiring. The other task will be for "Two Edge Separation", and you want to measure from the active (lead) edge of the master clock to the passive (trail) edge of your sync'ed pulse train. There's a reason NOT to measure to the active (lead) edge of your pulse train and it's because counters can only measure finite times of at least 2 timebase cycles. Whereas you would *like* to have an actual two-edge separation time of 0 between the lead edges. That just seems like the kind of detail that's gonna burn you sooner or later.
Let's just suppose the master clock is nominally about 1 Hz and your pulse train is nominally 100 Hz and 50% duty cycle so I can talk through details with some specifics. Whenever the two lead edges are truly sync'ed, you'll measure a 0.005 sec two edge separation time from the master clock to your pulse train's trail edge. If you measure slightly *less* than that, your pulse train is going just a little too fast and needs its freq slightly reduced. If you measure slightly more, then your pulse train is too slow and needs its freq slightly increased.
It is probably quite likely that you *cannot* expect to maintain perfect sync *without* constant monitoring and adjustment. Fundamentally, you can only produce pulses with high and low times that are an integer multiple of the 6601's timebase of 20 MHz. That card's oscillator won't be perfect, nor will it be utterly constant over temperature variations, etc.   So its idea of a perfect 100 Hz pulse train will in fact be very very close but not *actually* perfect.
And your ability to adjust the frequency away from a nominal 100 Hz will only be possible in discrete steps.
A 100 Hz pulse train takes 200000 cycles of the 20 MHz clock. If you adjust your square wave to take 199998 or 200002 cycles, you can produce a nominal freq of 100.001 or 99.999 Hz. Those are the smallest increments away from 100.00000000 that are possible with a 50% duty cycle.
Statistically, it's very unlikely that the frequency needed to perfectly match the external master clock is even *possible* to produce exactly. I think you need to *expect* an imperfect sync with continual subtle adjustments to your pulse train. If you watched the signals on a scope while triggering from the master clock, I think you should expect to see your pulse train oscillating back and forth by some small amount, perhaps in the microsecond realm.
Summary (for 1 Hz master clock, 100 Hz user pulse train at 50% duty cycle):
Measure two-edge separation from lead edge of master clock to trail edge of user pulse train. Use units of "Ticks" with 20 MHz timebase. Nominal expected value when sync'ed is (1/2)*(20 MHz / current user freq) = 100000.
Subtract measured ticks from nominal to produce your "error signal".
Use current error signal its recent history in a control algorithm to determine the amount of adjustment to make to your pulse train. Hint: it will probably NOT be correct to directly change the user pulse width by an amount equal to the error signal. I suspect that you'll want to pay closest scrutiny to the derivative of the error signal. Note also that the correct AMOUNT of adjustment will depend on the RATE at which you run your measurement / adjust loop.
Change user pulse specs on-the-fly.
Return to step 1.
Caution: Let's suppose your software measurement / adjust loop runs at a nominal 10 Hz. From the time you make an adjustment until the next time you do a measurement, your user pulse train will have generated almost 10 cycles with the recently-adjusted specs. If you weren't careful to make your previous adjustment subtle enough, you'll find that you now have a *larger* error of the opposite sign, and you are well on your way to instability.
   You need to do an adjustment that lets you expect your *next* measurement to have an error close to 0.
-Kevin P.

USB-6009 pulse train generation with digital output....

Hello!
I've bought a new USB NI-Card (USB-6009) and now I'm trying to adopt an old vi that uses traditional DAQ drivers. I wrote that vi for a PCI NI-Card (PCI-6024E), which has two counters to generate two pulse trains simultaneously. Now I've only one counter and that's why I'm searching for a good way to create pulse trains using a digital output! The pulse trains are both ranging between 100 Hz and 100 kHz.
I'm sure somebody has an idea how I can solve the probem in the best way
Kind regards,
Peter

You can't do it with this low cost board. Both digital and analog outputs are software timed only. The analog out is rated at only 150 samples/sec and the digital is about the same. You can't even use one of the counters because it is not a hardware timed counter output. It is an event counter only as an input.

How can I use the pulse train from a 6602 to trigger an niFGEN and niSCOPE on each rising edge of the pulse train?

Hello,
Here is my application: I need to use a 6602 counter/timer to generate a pulse train of certain frequency and duty cycle. On each rising edge of this pulse train, I need to output an arbitrary waveform on Ch. 0 of an niFGEN (5422) AND acquire data from CH. 0 of an niSCOPE (5124). I also need to synchronize the niFGEN and the niSCOPE to the same clock used for the pulse train (6602/ctr0). This process needs to continue until the user stops the system.
I can generate the pulse train using the 6602 just fine using ctr0, but the pulse train shows up on OUT0 by default. When setting up the niFGEN and niSCOPE to trigger on rising/positive slope edge, OUT0 is not an option for either device as a source for the digital rising edge (pulse train). The main options for both are PFI0-3 and RTSI lines.
Questions:
1.) Is there a way that I can direct the pulse train to a location (such as an RTSI line) where BOTH the niFGEN and the niSCOPE can use it as a start trigger for each rising edge? I noticed in MAX that a route can be made between ctr0's internal output and a trigger line and others. If this is a solution, could you please explain how to accomplish this?
2.) Once I configure the niFGEN and niSCOPE to be triggered on a digital rising edge, how can I effectively have this happen for every rising edge from the pulse train? In other words, can I just initiate the FGEN outside of the while loop and it will generate a waveform for each rising edge it sees at the source until the while loop is exitted?
3.) Is setting a reference clock for the niFGEN and the niSCOPE the same thing as synchronizing both devices using the same clock that generated the pulse train? It is not clear to me the difference, and why it would necessarily be useful.
Images of my current front panel and block diagram are attached. If you would rather have the actual VI's just let me know. Any help and/or explanation on this is greatly appreciated. Thanks in advance.
Attachments:
Front_Panel_Control.jpg ‏278 KB
Block_Diagram_Control.jpg ‏263 KB

Hello Cgifford,
Welcome to National Instruments Forums.
To output your signal to the PFI lines,
you can use external connectios between OUT0 and PFI lines. You can also use
the backplane to do so by routing into the same RTSI line.
1)
On the SCOPE and FGEN, the name of the
terminals are actually “PXI Trigger Line x/RTSIx” but on the 6602 you might
need to route the signal using the property:
You can also use the DAQmx route signal which perform the same opperation.
2)
This will depend on the frequency of
your pulse train. If this is lower than about 10 ms, then you can probably
place this on a loop and start and stop the acquisition every time. If the
frequency is higher than this, you will have to use:
- Scripting on the FGEN side (read more)
- MultiRecord Fetch (more information in the scope help file
section “Acquisition Functions Reading versus Fetching”).
3)
The short answer is yes. The longer one
might depend on how tight you need the synchronization to be (us, ns, ps). For
very tight synchronization, you should look into here.
Message Edited by Yardov on 06-18-2007 03:14 PM
Gerardo O.
RF Systems Engineering
National Instruments
Attachments:
property.JPG ‏7 KB

Multiple pulse trains

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