NI LabVIEW 2014 Digital Electronics FPGA Board Driver

Hello all,
When NI LabVIEW 2014 Digital Electronics FPGA Board Driver Release date?
Thanks.

Hi mlewis1973
We have no information regarding the next release of this driver yet. As you mention, the 2013 version is available, so, for now, the solution would be to use LabVIEW 2013 until R&D gives us an update regarding this topic.
Thanks!
WenR

Similar Messages

Digital Electronics FPGA Board with Xilinx ISE

Hi,
I've a design in Xilinx ISE. I Synthesized and created the Bit map file.
How can I export this bitmap file to the NI Digital Electronics FPGA is board? I tried using Adept to program, but the tool didn't detect FPGA board.
Thanks in advance.

Hello,
The Adept Program is something that is made by Digilent. This application isn't meant for being used with non-digilent FPGAs such as the one on the NI Digital Electronics FPGA Board. The FPGA on this board is made by Xilinx so you have to use Xilinx tools in order to deply files to the FPGA (assuming you're not using LabVIEW FPGA). Specifically, you should use the Xilinx iMPACT Software, version 10.x or later, which is part of the ISE WebPACK kit. You can get this software from www.xilinx.com/ise.
If you still have questions about deploying your files to the FPGA, you can refer to the following resource.
Xilinx iMPACT Examples:
http://www.ni.com/white-paper/8671/en/
I hope this helps!
Regards,
Cameron T
Applications Engineer
National Instruments

NI Digital Electronics FPGA Breadboard's UCF

Good day..i've been using Xilinx ISE 14.3 to program my NI Digital Electronics FPGA board and i want to use some FPGA GPIO lines placed on the Breadboard1(BB1) area...how can i create my UCF file to use this GPIO.??
Solved!
Go to Solution.

Hey Dominic,
I just want to be clear... if you're trying to use LabVIEW to target the board, you will need the LabVIEW FPGA Module. If you're just using ISE, you can use the UCF attached below to enumerate all of the pins on the device. Since our forum system won't let me upload a .ucf, I posted it as a .txt... just change the extension or copy/paste the pins you need into your project's .ucf.
Cheers!
TJ G
Attachments:
DEFB_PINS.txt ‏9 KB

Has anyone has developed a driver which uses labview to control an EPIX(R)D PCI Digital Video Capture Board?

We have an EPIX(R) D PCI Digital Video Capture Board from EPIX Inc. worked with Image Pro Plus and a
Kodak Megaplus 1.4 CCD Camera. This camera is an old model with Camera Control Unit. Now we use Excel Macro works with all of these software and hardware and the whole system works excellent. Now we intend to update the software to Labview 6.1, IMAQ vision builder and IMAQ vision. But we didn't find the driver to let Labview work with EPIX(R) D PCI Digital Video Capture Board. I have contactd Epix Inc. They said some customers have developed their own driver for labview and it works fine.But this company doesn't support this driver. It will be appreciated if anyone ca
n provide this driver for us. Thank you very much.

George. You probably don't have many options with the Epix board. However, if your Epix software enables you to save files to disk, then you can open them from LabVIEW and process them with Vision or Vision Builder.
Another option is to contact Graftek (www.graftek.com) or ImageMill (www.imagemill-tech.com). They have created drivers for third party image acquisition boards in the past and they may have one for your Epix board.
A third option, of course, is to upgrade your Epix board to an NI IMAQ board. Your sales contact within NI may even be able to give you a discount on the trade in, but I can't guarantee it.
Good luck!
Kyle V

How to use LabVIEW FPGA on Custom FPGA board other than NI products .....Also how to develop RTx DLL for a customised motion controller hardware

I'm using RTx, LabVIEW RT and LabVIEW FPGA.
The GUI is windows based. The motion control and FPGA are RTx based.
Is there any way to develop device drivers for the custom hardware in RTx. For example motion controller hardware, FPGA hardware, PCI hardware.
Is there a possibility to use custom FPGA boards to use with LabVIEW FPGA.
Please send me some links
Thanks
Bhoopathy
Take life as it comes! you may never know what's gonna happen Tommorrow

CODE WARRIOR Hello. I believe this question was answered in a previous post. Please let us know if you have any new questioins or if you need some clarification.
You are able to develop device drivers for your custom hardware using the NI Measurement Hardware Driver Development Kit.
However, it is not possible to use custom FPGA boards with LabVIEW FPGA. The FPGA boards have to be one of our R Series boards. Here are some links that should shed some light on the Measurement Hardware DDK.
Measurement Hardware Driver Development Kit Frequently Asked Questions
NI Measurement Hardware DDK (Driver Development Kit)
Please post if you have further questios.
Efosa O.
NIAE

What is the data throughput in labview. I want to use the parallel as acheap digital i/o to drive a stepper motor.

I am trying to use the parallel port on a win xp machine to send data a@ up to a 3k rate. This is for the the purpose of driving a stepper motor. I have tried the port.out vi and placed this vi in a loop and it on a scope it looks like I am limited to a a 200hz rate. What am I doing wrong??? Can labview do this or is it too slow ???
Thanks

snook wrote:
> what is the data throughput in labview. I want to use the parallel as
> acheap digital i/o to drive a stepper motor.
>
> I am trying to use the parallel port on a win xp machine to send data
> a@ up to a 3k rate. This is for the the purpose of driving a stepper
> motor. I have tried the port.out vi and placed this vi in a loop and
> it on a scope it looks like I am limited to a a 200hz rate. What am I
> doing wrong??? Can labview do this or is it too slow ???
Basically the way the Port I/O VIs are implemented they call through a
device driver for each port access. This slows down the maximum port
accesses to something like 1000 times per second depending on the speed
of your CPU.
There is a way to do it faster but that is a little more trick
y. The
idea is to use a device driver to enable particular port addresses to be
accessed directly from the application level instead of always going
through the kernel.
I have written such a VI library and accompagning DLL and device driver
and made it available on OpenG. It is not yet part of the standard
binary distribution packets so you will have to get it from the CVS
repository.
Go to:
http://cvs.sourceforge.net/viewcvs.py/opengtoolkit/portIO/built/portio/
and download all the files in there including the ones in the
subdirectory "ogportio.llb" and if you like "docs"
If you want the nitty gritty technical details you can also look at
http://cvs.sourceforge.net/viewcvs.py/*checkout*/opengtoolkit/portIO/c_source/Description.htm?rev=1.5
On my 866 MHz Pentium mobile I can increase the number of port accesses
in this way from 440 ms for 4000 read byte port accesses (100us ms per
access) to 20 ms for the same number of read accesses (5 us per access).
Rolf Kalbermatter
Rolf Kalbermatter
CIT Engineering Netherlands
a division of Test & Measurement Solutions

Como puedo instalar ISDB-T/Tb Digital Video Signal Generation Toolkit - MaxEye Technologies en labview 2014

Hola me gustaria que me ayuden con un problema que tengo, descargue ISDB-T/Tb Digital Video Signal Generation Toolkit - MaxEye Technologies evaluation pero cuando lo quiero instalar me aparece un mensaje diciendo que primero debo instalar labview 2012 pero yo tengo labview 2014, como puedo instalar esta herramienta sin tener que cambiar la version de mi labview?

Saludos Mafilu,
Gracias por utilizar los Foros de Discusión de National Instruments, con respecto a tu consulta creo que lo mejor será que contactes directamente al equipo de soporte de MaxEye Technologies para corroborar si existe alguna necesidad especial, o bien, si tienen alguna alternativa.
Support Information
For technical support, contact MaxEye Technologies at:
Phone: +91-80-2527-0024, +91-94-4806-7717
Email: [email protected], [email protected]
Web: maxeyetech.com
Quedo al pendiente, saludos.
David P.
National Instruments
Applications Engineer
www.ni.com/soporte

Site / Pin addresses for DAC on NI Digital Electronics Board

My advanced DE students are trying to build a circuit capable of communicating with the DAC on the NI Digital Electronics Board.
We have things to the point where we have a solid data stream, synchronized with our serial clock, and timed correctly relative to the DAC_CS pulse. It all looks great on our oscilloscope. The one thing we are missing is the sites the signals are supposed to be mapped to in the Xilinx PlanAhead software.
For example, LED0 is C11, LED1 is D11, SW0 is J11, SW1 is J12, etc...
The signals we need to be able to control on the DAC are:
DAC_CLR, DAC_CS, SCK, and SDI.
Thanks,
-Bret Wood
Solved!
Go to Solution.

Ooops, found it myself.
The master file was C:\Program Files\National Instruments\Circuit Design Suite 11.0\pldconfig\DEFB.ucf
The DAC related locations are:
SCK           R4
SDI            P3
DAC_CS    N12
DAC_CLR P13
Hope this helps someone else too.
-Bret Wood

CanOPEN cRIO-9067 & LabVIEW 2014 support

Hello,
We have cRIO-9067 and NI 9881 CANOpen communication module.
According to the NI 9881 product description page the module should work with cRIO-9067. However, the latest NI-Industrial Communications for CANopen 1.0.3 doesn't support LabVIEW 2014 and NI RIO 14.0. This means we can't use cRIO-9067, can we? If so, when the next release of the driver will be availiable? Will it work with cRIO-9030?
Thank you in advance,
Nikita.
Nikita Prorekhin
Certified LabVIEW Developer
DigiMetrix GmbH
web www.digimetrix.com
Solved!
Go to Solution.

Hi Nikita,
This is an error on the webpage. Currently, it should actually read:
The NI 9881 module requires the NI cRIO-911x/9068/908x chassis and the LabVIEW FPGA Module.
Support for the 906x and 903x targets will come with the NI-Industrial Communications for CANopen 14.5. Typically, the release is around the time of the LabVIEW 2014 SP1 release. I apologize for the inconvenience, and have reported this to the person in charge of the page to correct this error.
Thank you!
Matt S.
Industrial Communications Product Support Engineer
National Instruments

FPGA Board CCA 193426B-01L

Trying to find a complete User Confirguration File (UCF) or a schematic showing the mapping of the Spartan chip pin outs for the FPGA board devices and I/O.
Several years ago, at least 5, the Philadelphia School District purchased the NI FPGA Boards that actually went unused until recently and are now being integrated into a Digital Electronics (DE) Course that will include the FPGA Board in various DE projects. To fully utilize the I/O and devices on the board itself we require User Configuration File data and/or a circuit schematic that will identify pin out connectivity from the embedded Xilinx FPGA to the various devices on the board (example Rotary Switch). Some of the data is included in information we were able to find or already had (e.g. http://www.ni.com/pdf/products/us/cat_defpga.pdf,http://www.ni.com/pdf/manuals/372809b.pdf, http://www.xilinx.com/support/documentation/user_guides/ug385.pdf), but our information is incomplete. A complete UCF or a schematic showing the mapping of the Spartan chip pin outs to usable devices on the board and its I/O pins/ports would greatly facilitate use of the board in our classroom projects.
I may be contacted directly via the email above or, you may reach the school and ask for me or Mr. Scott Koehler, Engineering Technology teacher, please see the attached link for the school: http://carver.phila.k12.pa.us/
We currently have ten (10) of the NI FPGA boards, which may at this point be dated, but still quite usable for school purposes. We would like to integrate these boards to introduce students to FPGA technology, and will expand the equipment base and course breadth as we get the course content established.
Chip: Xilinx Spartan XC3S500E
Board: CCA 193426B-01L
Solved!
Go to Solution.

Fernando,
Greatly appreciate your responsiveness.
We will be using Multisim, and have it installed, as part of the DE Course, but we also want to teach students using C-Language/Verilog/VHDL a variety of tools, and the JTAG programming port directly, and want to be able to direct I/O from the Spartan FPGA to a variety of devices on the CCA or connected externally. So, I guess we want to get under the hood a bit, teach the tools comparatively, and complement Multisim usage, which is a great tool.
This board is a few years old, I am not sure if it is the current version or still in production. Is there a complete UCF or a schematic that will identify Spartan pinouts to CCA devices and I/O? What we are doing is updating, expanding the course and integrating the FPGA (that has gone unused until now) and other devices.
We have ten of the FPGA boards now.
Chris Speck, PE (Retired)
Science, Math, & Engineering Technology Teacher (PA)

DE FPGA Board not Connecting

I am using DE FPGA board with NI ELVIS II, and LabVIEW 2012. I have searched in the Discussion forum and got the latest driver software (5.2) for the board.
But when I start running my FPGA VI , after successful compilation and generation of Bit file (after synthesis) the error message shows "Communication cable is not detected"
What is the problem?
** My board is working fine with Xilinx ISE.
Attachments:
XilinxLog.txt ‏236 KB
Screen Shot.docx ‏1642 KB

Thanks for your reply,
But I have already got the problem solved.
I don't know how, but one day It suddenly worked!! then I tried the same procedure in another computer, there also it worked.
I think, the problem was that, the previous version of driver was installed in my laptop, after I have uninstalled it, the device worked!! I am really surprised with the procedure !! But It happened !!

NI Digital Electronics Board DAC and ADC access from Multisim

Is it possible to use the ADC and DAC functionality of the NI Digital Electronics Board from a circuit designed in Multisim?
I would like to have my students be able to digitally sample an audio input, perform transformations on the data stream, and listen to the effect. Nothing particularly fancy.
Thanks,
-Bret Wood

Hello,
In order to use the ADC/DAC you need to define a protocol and this goes beyond the scope of the PLD schematic in Multisim.
LabVIEW can be used to accomplish this, there are some examples that you can use as reference, they can be found in the NI Example Finder.
Regards,
Fernando D.
National Instruments

Compile 9076 with LabVIEW 2014 Worked good with 2012 SP1

An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:
Error 7 occurred at Open VI Reference in nirviOpenVIRefByNameOrPath.vi->niFpgaRemapObjsAndListIfUnderXNode.vi->niFpgaRemapObjsHandleXNodeSubErrors.vi->nirviMassageErrorList.vi->niFpgaErrorDialog_ParseErrors.vi->niFpgaErrorDialog_ReadErrorData.vi->niFpgaGenerateCode_ErrorDialog.vi
Possible reason(s):
LabVIEW: File not found. The file might be in a different location or deleted. Use the command prompt or the file explorer to verify that the path is correct.
VI Path: C:\Program Files\National Instruments\LabVIEW 2014\rvi\CodeGenErrorUtilities\Diagram Constant
All text parsed:
<CodegenErrorList>
          <CodeGenErr>
            <ErrorCode>-64001</ErrorCode>
            <DynamicText>
              <TreeLineInfo>
                <TreeInfo>
                  <TreeID>1</TreeID>
                </TreeInfo>
              </TreeLineInfo>
            </DynamicText>
          </CodeGenErr>
          <CodeGenErr>
            <ErrorCode>-64001</ErrorCode>
            <DynamicText>
              <TreeLineInfo>
                <TreeInfo>
                  <TreeID>1</TreeID>
                </TreeInfo>
              </TreeLineInfo>
            </DynamicText>
          </CodeGenErr>
          <CodeGenErr>

Hi Nieman,
You have the right compilers for your FPGA targets, based on KB 609GUVBT.
Error -64001 indicates that there is an issue with one of the nodes in your VI. Since you are able to compile a blank FPGA VI, then you should try to identify the node that is causing this problem. When trying to pinpoint this node, I’d recommend executing your FPGA VI with simulated I/O on the development machine, as described in KB 3W6EFRLX,
Also, are you able to reproduce this issue when running one of the LabVIEW Example Finder FPGA VIs that targets your NI 9076? You can find these examples in the Example Finder's Hardware Input and Output>>CompactRIO section.
Regards,
Tunde S.
Applications Engineer
National Instruments

Western Digital USB3 external hard drive (attached to new MBP Retina) seems to randomly "eject" itself when I'm trying to back it up via time machine. When this happens, I can't even shut my machine down properly. Ideas?

The backup process will run for sometimes 30 minutes or more. But, it's as if, at some point, the drive just can't be found. I get the message "this drive was ejected improperly". When this happens: my machine won't shut down, disk utility won't run. I have to press and hold the power button to force a shut down. Any ideas what's going on here? A MBP Retina issue? A USB3 issue? A western digital issue (although this drive has been functioning fine on old MBP)?
Thanks!

When you say that you've applied the latest 'patch,' I'm assuming that you mean the latest (July 18) software update for mid-2012 models? It was supposed to address some of the problems with the USB 3.0 ports. I don't think that, in most cases, it's a problem with the drives themselves (USB 2 or 3), rather it seems to be a port problem.
If it wasn't fixed for you using the July 18 Software Update the only thing I can recommend at this point is to see if Mountain Lion - soon to be released - will be able to fix the problems. If not, I would take your unit back to the Apple Store and let them know that you are continuing to have problems with the USB 3.0 ports. They may offer to switch out your logic board, etc.
Good luck,
Clinton

What is the best method to manage a digital I/O board from TestStand?

Hello,
I'm a beginner with TestStand (3.5).
I want to create some Step types in CVI to write/read to a digital I/O board (PCI6509).
What is the best way to do this?
I don't know if it is better to build 2 big groups (i.e 48 input / 48output) and read/write all simultaneeusly or drive the lines one by one.
I would like to create a reusable code, also for multithreading.
Any help will be appreciated
Thanks
baloss

Hi Baloss,
in the general point of view there is no "best" method to do this. Again, there are advantages in both ways - it is depending on the Test you want to do.
I would not recommend to create Tasks and do all the writing and reading in different steps. Sure it might be faster if you are able to get it work, but to get in work it will take a bit of effort. The Task Reference is not Global, so if you pass the Reference to TS and unload the VI from Memory, your Reference will not be valid anymore. If your using Multithreading in some ways you must handle the Resscource so that the Hardware is not blocked by another Task. You see it will be tricky.
I would recommend to write down, what Tests has to be done. Than you can define steps which are as general as possible. So if you want to read a line in one test and 5 lines in another, it could be a could idea to define a step in which you read a hole port into a array and depending on a input array with a "wanted line pattern" you can pass the results of 1 , 2 or more lines needed to TS.
You have one step in which you can perform every read request depending on a input from TS.
The Step will be self-contained and reusable and you can create a Report with the Read-Results.
The same way I would recommend for Write Operations. All with focusing on the Test Results you want to get.
I really hope that helps a bit.
Stefan
NIG

NI LabVIEW 2014 Digital Electronics FPGA Board Driver

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