Number of elements in target to host DMA FIFO

Hi everyone,
I'd like to transfer a set of datapoints from a FPGA to a RT-host controller using a DMA fifo. If I use the "Get Number of Elements to Write" function on the FPGA target, do I get the total number of elements in both buffers, or just the one on the FPGA-target?
(see http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/)
Solved!
Go to Solution.

What type of data do you want to transfer over the FIFO? As in how many bits does each sample contain.
The reason I ask is because you can take a bit packing approach.
Lets take for example you want to take two samples of a measerment both samples are 32 bit and then send the data as a set to the processor.
If you just dump the data into a single FIFO you may lose track as to what was the rising edge, or falling edge data, or if the two samples you got from the FIFO are even from the same dataset.
To fix this use bit packing technique.
On the FPGA merge your two 32 bit data sets into one 64bit dataset.
Set your FIFO to 64 bits.
On the processor side of things all you need to do is read one 64bit dataset from the FIFO.
Use the split data to break the 64bit into two 32bit data fields.
Now you have your two data samples, and you can be garentee that it is from the same dataset.
If the sum of the data bits exceed 64 bits (the limit of the FPGA FIFO) then you will need to migrate to a more complex bit packing data schema where the data is split up among multiple 64bit datafields, with a defined bitfield header and identifier. For example the first 5 bits of the 64bit data identifies that this data block is 1 out of X data blocks, that when combinded together and reasembeled per the schema will represent your data..
I hope this helps.

Similar Messages

FPGA target to host DMA transfer speed

Hello,
------------Task summary:
I'm currently working on a data acquisition-heavy project using a PXIe chassis system (plus a host computer), see below for the components.
PXIe-PCIe8388 x16 Gen 2 MXI-express (controller)*
PXIe-1082 (chassis)
PXIe-7966R (FPGA)
NI 5772 (AC version, IO Module)
*note: the controller is connected to a PCIe port on the host computer with the full x16 bandwidth.
For my application, I need to acquire a fixed number of samples (16000) from each channel of the IO module at a fixed sampling rate (800MS/s). Each acquisition will be externally triggered at a fixed frequency, 50kHz. The number of acquisitions will also be fixed. Right now I'm aiming for about 90000 acquisitions per session.
So in summary, for each acquisition session, I will need (16000 samples per acquisition) * (90000 acquisitions) * (2 AI channels) = 2.88e9 samples per acquisition session.
Since each sample is transferred as a 16-bit number, this equates to 5.76GB per acquisition session.
The total time per acquisition session is (90000 acquisitions) / (50kHz per acquisition) = 1.8 seconds.
--------------Problems:
I'm having problems transferring the acquired data from the FPGA to host. I think I'm seeing an overflow on the FPGA before the data is transferred to the host. I can go into more detail pending an answer to my questions below.
--------------Questions:
I want to ask a few general questions before posting any code screenshots. Assuming my math is correct and the host computer 'good' enough, is it theoretically possible to transfer data at my required throughput, 5.76GB/1.8seconds = 3.2GB/s using the hardware that I have?
If it is possible, I can post the FPGA and host VIs that I'm using. If not, I will have another set of problems!
Thanks,
Michael

thibber wrote:
Hi Michael,
I have a few questions / observations for you based on your post:
First, you mention that you are using the PXIe-PCIe8388 x16 Gen 2 MXI-express. This is only compatible with the NI RMC-8354, so when you mention the streaming speeds you are looking to acheive, is this streaming back to the RMC, or to something else? Is the NI RMC-8354 the host computer you are mentioning?
When it comes to streaming data with the NI 5772 and PXI 7966R, there are a few different important data rates. First, the NI-5772 can acquire at a maximum rate of 1.6 GS/s with 12 bit resolution = 2.4 GB/s. This is only if you are using 1 channel, for 2 channels the rate is halved. Are you planning on using 2 separate 5772 and 7966Rs?
The 7966R can stream data at a maximum rate of 800 MB/s, so we have a data rate coming into the FlexRIO's FPGA (2.4GB/s) and going out of the FlexRIO's FPGA (.8 GB/s). The data that isn't being sent back to the host accumulates in the FPGA's DRAM. Lets say we have all of the FPGA's DRAM available to store this data (512 MB). Our effective accumulation rate is 2.4 - 0.8 = 1.6 GB/s, so our FPGA is going to fill up in about 1/3 s, streaming a total of 0.8+0.512 = ~1.3 GB back to the host before saturating and losing data.
There are a few options, therefore, to reach your requirement. One might be duplicating your setup to have more cards. 1.3 GB x 3 = 4GB, which meets your need. Also, the 7975R can stream data back to the host twice as fast and has 2GB of DRAM onboard, so you could store more data and stream faster, therefore meeting your requirement.
I hope that this information helps clarify what concerns come into play for this type of application. Please let me know if anything above is unclear or if you have further questions.
Thanks for replying. To answer your first question: I'm transferring to a desktop computer. The controller is able to connect with a PCI express x16 slot in the desktop computer. I'm not sure how to technically describe it, but the controller plugs into the PXIe chassis, then there is another card that plugs into the host computer's PCI express x16 slot, and finally there is a large cable that connects the card in the host computer and the controller.
For your second paragraph: the reason I used 16-bit numbers in my calculations is because that's how the data is handled in the FPGA after it has been acquired (assuming I keep it as an integer), is that correct? Then it's packed in chunks of 4 (one U64) before being inputted to the target to host FIFO (that's how the NI 5772 examples do it). Right now I'm only using one FPGA and I/O module, and I'm using both AI channels (I need to simultaneously sample two different inputs).
I might be able to live with half of the sampling rate, 400MS/s for both channels, if that means I will be able to acquire a larger amount of data. Getting another FPGA and IO module is also an appealing option. It depends on what my advisors think (I'm a graduate student), and if they want to buy another FPGA and IO module.
Questions:
I have a question about the 7966R vs the 7975R that you mentioned. I could probably find the information in the specifications, but I figured I would just ask you here. Is there any advantage to using the 7966R over the 7975R in terms of programmable logic elements? From what I could quickly read, the 7975R has more DSP slices and RAM, but does it have less general purpose logic blocks than the 7966R? The reason I'm asking is because the project that I'm working on will eventually involve implementing as much signal processing on the FPGA as possible. But obviously figuring out the acquisition part of the project is more important right now.
The other question I have is related to something nathand said in response to my first post. Is using multiple target to host FIFOs faster than using 1 target to host FIFO (assuming the combined sizes are equivalent)? I noticed that the FPGA has a max of 16 target to host FIFOs. Does each target to host FIFO reserve some amount of bandwidth? Or is the total bandwidth just divided by the amount of target to host FIFOs that I use in a given FPGA VI? Ex: If I only define 2 target to host FIFOs, each would have half of the total bandwidth, if I define 3 target to host FIFOs each would have 1/3, etc.
Hi Michael,
A few updates to my previous post:
First, I think I could have explained the sampling rate a bit more clearly. Using 2 channels instead of 1 means that each channel will have half the sampling rate (800 MS/s), but the total acquisition rate will still be the same (1.6 S/s).
There are some other options you might want to look into as well regarding your acquisition. For instance, is it acceptable to use only the 8 most significant or least significant bits of your measurement? Or to discard a section of your acquisition that is irrelevant to the measurement?
Also, if you do end up wanting to look in the direction of a 7975R, you would also want to likely switch to a 1085 chassis to fully utilize the improved streaming speeds. The 1082 has a limitation of 1 GB/s per slot, while the 1085 can achieve up to 4 GB/s per slot.
I look forward to hearing what other observations or concerns arise in your testing.
Andrew T.
National Instruments
I'll go ahead and respond to your latest response too. Thanks again for your help.
I think I understand the streaming rate concept. I'm not using time interleaved sampling. My application requires using the simultaneous sampling mode. I need two channels of input data.
Unfortunately I don't think I can sacrifice on bit depth. But for right now I can probably sacrifice half of the sampling rate, and reduce my acquisition duty cycle from 100% (constantly streaming) to 50% (acquiring only half of the time). My acquisition rate will still need to be 50kHz though. I'm planning to compromise on sampling rate by summing pairs of data points instead of simply decimating, and then transferring the data to the host.
Questions:
We (my advisors and I) think that the summing pairs approach would preserve more information than simply throwing away every other point. Also, we can avoid overflow because each 16-bit number only contains 12-bits of actual information. The 16-bit number will just need to be divided by 16 before summing because the 12-bits of information are placed in the 12 MSBs of the 16-bit number. Does that sound right?
As for upgrading the hardware, that would be something I would need to discuss with my advisors (like I said in my above response to your previous post). It would also depend on any exchange programs that NI may have. Is it possible to exchange current hardware for some discount on new hardware?

How to decide the maximum number of elements for DMA FIFO in R series FPGA

Greetings!
I'm working on a project with NI R series PCIe-7842R FPGA board. To achieve fast data transfer I'm using target-to-host DMA FIFO. And to minimize the overhead, I'd like to make the FIFO size as large as possible. According to the manual, 7842R has 1728 kb (216KB) embedded block RAM, i.e., 108,000 I16 type FIFO elements available in theory (1728,000/16). However the FPGA had compilation error when I requested such amount of elements. I checked the manual and searched online but couldn't find the reason. Can anyone please explain? And in general, what's the max FIFO size given the size of the block RAM?
Thanks!

Hey iron_curtain,
You are correct that moving larger blocks of data can lead to more efficient utilization of the bus, but that's almost certainly not the most important factor here. Assuming of course that the FIFO on the FPGA is big enough to avoid overflows, I'd expect the dominant factor to be the size of read performed on the host. In general, larger reads on the host lead to improved throughput, up to the speed of the bus. This is because FIFO.Read is a relatively expensive software operation, so it's advantageous to make fewer calls to get the same amount of data.
Note that the larger your call to FIFO.Read the larger the host buffer needs to be. Depending on your application, it might need to be several times larger than the read size. You can set the buffer size with the FIFO.Configure node.
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/ explains the various buffers involved. It's important to note that the DMA Engine moves data asynchronously from the read/write nodes on the host and fpga.
Let me know if you have any questions about any of this.
Sebastian

FPGA to HOST DMA

I am trying to record rising edge timestamps of a digital signal input to a spreadsheet using a CRIO. I have been getting some bad data elements recorded (although there are periods without faults). This is perhaps the input signal but i would be greatful if someone could check my VI's for any obvious mistakes.
I would also like to do the same with another input signal. Should i use 2 FIFOs, as below?
Many Thanks
Erny

ern,
Here are some thoughts.
Make sure that your FIFO type is Target to Host - DMA. If you use more than one, make sure that the DMA Channel is unique for each (0 and 1 for instance). Check the depth to make sure that you are not running out of space in the FIFO. Your FPGA code looks ok to me.
In the GUI, you are specifying to read 1023 elements at a time. Is your FIFO this same size? This means that you will most likely always miss edges as the GUI will not read out the data until 1023 data points are present. You are trying to stream edge timestamp information to the GUI so you have to stay ahead of the FPGA or you will miss data. You could code your GUI so that you use a shift register to pass the number of Elements Remaining back as an input to the read operation as the Number of Elements to read. You could seed the shift register with a value of 500 (or something like that) as the initial read. You would also have to make sure that if the number of elements remaining was too small (or zero) that you set it to some minimum or you may read data out one point at a time depending on your edge rate.
In you GUI loop, you are writing to a file too. You might want to use a producer consumer type architecture to read in the data. One thread would read out the fifo as you currently have. A second thread would write the data to a file. You would pass data from the fifo thread to the file writer thread with a queue.
Hope this helps!
-cb

Regarding DMA fifo.

My goal is to transfer data to target at its rate. I have the data(array) on the host VI and wants to transfer this data onto the target using a DMA FIFO.
To perform this, i am using two DMA FIFO one at channel 0 which is a host-to- target scoped and the other at channel 1 which is target-to-host scoped.
Depending on the type of the FIFO, i am peforming read and write on those. But i cant find the data on the second FIFO reading at host side.
Can anyone help me in synchronizing the host and the target?

OK give me all information on your project.
Version of LabView.
Details of each target.
Rate of transfert
and if possible an example of your code.
Thanks
Benoit
Benoit Séguin
Software Designer

How can i decide the depth of all3 DMA fifo's are used as target to host at RT contoller side(host)?

Hello,
I am using all DMA fifos,I want to acquire data from 3 AI modules upto 50 khz frequency.Sampling rate can be varied according to application.
please suggest me how should i allocate memory of my RT controller for those DMA fifos?I am also facing one problem, I am using 3 time deterministic loop with different different priorities,each time loop has one fifo where data is reading with polling method(first fifo.read=0 then againg fifo.read=remaining elements).and each time loop has been interact to host vi with global varibales.those global variables data update from normal time loop.can anybody suggest that this procedure is right or not.if my problem is not much clear i will again explaing my query with snapshot of my application.
Pratima
*****************Certified LabView Associate Developer****************************

You wouldnt need to allocate memory separately on your RT Controller for the FIFOs. You need to create a FIFO under your FPGA target and use the FPGA interface VIs in your RT VI to access the DMA FIFO. You would need to use the FPGA interface invoke method VI to access your DMA FIFO.
As for the other questions, I would recommend you to create a separate post the RT section of LabVIEW so that you can get a faster response to your questions.
I hope this helps!
Mehak D.

DMA FIFO number of elements to read mismatch in FPGA and RT

Hi all
I am using myRIO , LV14 to run my application.
Application: I have to continuously acquire data via FPGA and process in RT host once every 2000 samples are collected. I use DMA FIFO (size 8191) to acquire data, use timeout property at the FPGA to eliminate buffer overflow. I had followed cRIOdevguide to implement this part. A snippet of what I have implemented is attached. Whole code runs in SCTL at 50MHz.
Issue: Twice or thrice I encountered with this strange behaviour, that the FPGA FIFO is giving continous timeout and the RT is unable to read the FIFO. The number of elements to write propery in FPGA VI gives 0 showing that FIFO is full and no more can be written, but at the RT, elements remaining is giving 0, hence it is reading 0 (no) elements.
Workaround: I put a case where I will write to FIFO (as per the code) and if the number of elements to write is nonzero. It seems to work fine, as of now.
What confuses me is that my FPGA VI says that FIFO is full (FIFO number of elements to write = 0) and gives a timeout error, but RT VI says that number of elements remaining in FIFO is 0 and hence no data is read. Any idea why it is so? My FPGA and RT VIs continues to run, but with no data being acquired or read.
I saw this behaviour within minutes after running the code. Any idea as to why it is happening? I am trying to reproduce the behaviour and will update if i again encounter with it. Sorry, I cannot post my code here, but i guess the code snippets explain it to some extend.
Thanks
Arya
Edit: Even with the mentioned workaround, the problem persists, now that the FPGA does not write to FIFO at all. And the RT VI is not able to read any elements as it sees 0 elements in the FIFO. The FIFO continues to be in timeout state. So i guess the problem is with the RT side.
Solved!
Go to Solution.
Attachments:
cRIOdevguide_FIFOreadwrite.PNG ‏107 KB
FPGA_FIFO_write.PNG ‏41 KB
RT_FIFO_read.PNG ‏39 KB

Hi Nathan
Yes, I could have replaced it with an OR. Regarding my application, I want to acquire data in chunks of 2000 samples. If at all I receive a timeout error, I want to discard that chunk of 2k samples and start all over again. So my logic was like this, I acquire the data, if there is a timeout, the reset is triggered, and the system waits to comeback from reset, and it starts acquiring again. Btw, I tried removing the multiple FIFO reads in RT, but the error is still the same.
I have a small doubt as well, if I do not want to obtain stale data at alI, I would just check if timeout occurs, empty my FIFO and start acquiring data again (no reset button), isnt it? This was my original logic, but I saw that after a while, it stopped acquiring data and timeout led was on. I was thinking that FPGA and RT was simultaneously trying to acquire FIFO which might cause timeout. Somehow, I now feel that, as you have pointed out, my code is overly complicated. I will modify it and update the results. Thank you!
Arya

Passing data from RT host to FPGA through DMA FIFO

Hello,
I am trying to write some data from an RT host to FPGA target using DMA FIFO then process this data and then read them back from the FPGA target to the RT host through another DMA FIFO. I am working on NI PXIe chassis 1062Q, with NI PXIe-8130 embedded RT controller and NI PXIe-7965R FPGA target.
The problem I am facing is that I want to send three different arrays, two of the same size and the third one with different size, and I need the smaller one to be sent to the FPGA first. I tried using flat sequece with two frames in the FPGA VI. In the first frame I read and write the first array in a while loop which is finite (i.e., finite number of iterations). The second frame contains the process of reading and writing the second two arrays (of the same size) in a while loop that can be finite or infinite (according to a control). The problem is that this didn't work. The 2 arrays are displayed on the front panel of the RT host VI and are working fine, however, the array that should have been read in the first sequence doesn't show up on the front panel of the RT host VI. This doesn't make sense because if it is not passed from the host to the fpga and vice versa then the second frame shouldn't have been executed. Note that I am wiring (-1) to the timeout to block the while loop iterations till the passing of each element is complete. Thus the first while loop has 3 iterations only. Could someone help me undersdtand why this happens and how to solve this problem?
I am attaching a picture of both the host and the fpga vi.
Thank you.
Solved!
Go to Solution.
Attachments:
RT host vi.png ‏102 KB
FPGA vi.png ‏28 KB

No need to initalize the arrays with values that you will immediately overwrite. Here's what I believe to be equivalent code:
The array outputs should be wired directly to the FPGA FIFO writes. Do not use local variables when you can wire directly.
If you know that you want to transfer the Temp Data Array first, why not make your code do that? Eliminate the sequence structure, and put the functions in the order in which you want them to execute. Use the FPGA reference and error wires to enforce that order. You might consider writing the Temp Data Array, reading it back, then writing the Real and Imag A arrays, to see if that gets you the results you expect. Run the code in simulation (in the project, right-click on the FPGA target and execute on the host with simulated IO) so that you can use execution highlighting and probes to see what is happening. Wire the error wires through and see if you get an error anywhere. Make sure you're not missing something simple like looking at the wrong starting array index.

Add file name to the element in target message

Hi all!
I try to configure scenario:
Get all files from directory (it will not be the same number of file every time) and mapping this file to the ERP system. I use File adapter to do this. But what Is necessary I need to mapp the file name to the element in target message.
I mean: When I have got the RFC structure imprted from ERP and there I have got the element "filename". I would like to put the file name of file which I mapping to this element. Next put the all file contents with file name to the ERP table.
It is possible to do that??
I found in sap help that I can keep file name in the message header to get the same target file name, but I wont to put file contents (with file name) to the ERP table not to another file.
THX for all your opinions.

The DynamicConfiguration fin inbound message:
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
- 
- <SAP:DynamicConfiguration xmlns:SAP="http://sap.com/xi/XI/Message/30" xmlns:SOAP="http://schemas.xmlsoap.org/soap/envelope/" SOAP:mustUnderstand="1">
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="Directory">/usr/sap/PXD/put/archive</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="FileEncoding">ISO646-US</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="SourceFileTimestamp">20061212T121622Z</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="FileType">txt</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="FileName">200610.TXT</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="SourceFileSize">124</SAP:Record>
</SAP:DynamicConfiguration>
and for Response:
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
- 
- <SAP:DynamicConfiguration xmlns:SAP="http://sap.com/xi/XI/Message/30" xmlns:SOAP="http://schemas.xmlsoap.org/soap/envelope/" SOAP:mustUnderstand="1">
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="SourceFileSize">124</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="FileType">txt</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="SourceFileTimestamp">20061212T121622Z</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="FileEncoding">ISO646-US</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="FileName">200610.TXT</SAP:Record>
<SAP:Record namespace="http://sap.com/xi/XI/System/File" name="Directory">/usr/sap/PXD/put/archive</SAP:Record>
</SAP:DynamicConfiguration>

How to get the number of elements in a tilelist

I'm writing test cases for a flex application using FlexSelenium and I need to get the number of elements displayed in the tilelist.
I know that that the tilelist is fed by an array. but i can't access that array from my test case.
Can anyone tell me how I can get the number of elements in a tilelist on the application? which property of the tilelist can provide that number?

try tileList.dataProvider.length;

How to get the number of elements in DB

Could you tell me how to get the number of elements in DB??
My code to get the number is below, but I think it is not efficient
DB->cursor(DB, NULL, &cursorp, 0);
while ((ret = cursorp->c_get(cursorp, &key, &data, DB_NEXT)) == 0)
count++;
--------------------------------------------------------------------------------------------------------------

Hi,
The most efficient way to get a count from the database is using the DB->stat API (http://docs.oracle.com/cd/E17076_02/html/api_reference/C/dbstat.html)
The code will be something like:
        DB *dbp;
        DB_BTREE_STAT *statp;
        int ret;
        /* Print out the number of records in the database. */
        if ((ret = dbp->stat(dbp, NULL, &statp, 0)) != 0) {
                dbp->err(dbp, ret, "DB->stat");
                goto err1;
        printf("%s: database contains %lu records\n",
            progname, (u_long)statp->bt_ndata);
        free(statp);The code comes from the example included in the distribution at examples/c/ex_btrec.c
If the database isn't a btree, you should update to the appropriate statistics structure and field.
It's worth noting that retrieving the count is never a "cheap" operation. The count is not stored in the database - since doing so introduced a single point of contention that creates a bottle neck.
Regards,
Alex Gorrod
Oracle Berkeley DB

Number of elements at logical level / odbc driver

Hi everyone,
I'm new in BI area and I cannot understand one basic thing.
I study documentation about BI server, exactly chapter about "creating dimensions" and I'm confused about setting "number of elements at logical level"
It looks for me that "number of elements at logical level" is static.
What will be when someone update data in the table and number of elements will be different than number of elements in our logical level?
example:
current column with distinct values:
channel_desc:
direct sales
tele sales
catalog
internet
partners
in this case I set number of elements at logical level 5.
after a while some update data in the table and our column looks (see below)
column after update with distinct values:
channel_desc:
direct sales
tele sales
catalog
internet
partners
others (added value)
Does it mean that I have to change it to current numbers of elements?
I'm sure that this is misunderstanding in my case, but I don't know where?
Second problem which I have:
BI with oracle database is on linux
client software on windows
I can import data from database like sybase or flat files to the physical model, I can view data, but when I create whole model (physical, bussines model and mapping, presentation) and I try access data from "Answers" I have this error:
"Data source name not found and no default driver specified"
regards
Bart

Number of elements is just an indication used by the BI Server (e.g. when generating LOV's in Answers). It won't cause any problems when it doesn't hold the exact number of elements available in the dataset.

Number of elements - Dimensional Hierarchy

Hi,
In a *'Dimensional Hierarchy'*, while creating a new *'Parent level'*, a 'Logical Level' dialogue box prompts for entering *'Number of elements at this Level'*+. What is its significance ?
What is achieved by+ *'Number of elements at this Level'* +?+
Thanks in Advance & Regards,
Deeba

Hi deeba,
Its not mandatory to specify the number of elements in hierarchy....if you wont mention also by default it takes the value of 1.....Above vino gave you the link for explanation.
Hope it helps you...Award points and close the thread.
By,
KK

Number of elements to be defined at logical level

In the Business Model and Mapping layer, dimension >Logical Level >> number of elements at this logical level
I have come across two different version of how to deal with this
First version - From the OBE and the admin server guide it says "The number does
not have to be exact, but ratios of numbers from one logical level to another should be accurate".
Second Version - a question from asked about what defines the number at the level as best practices
To set the number of elements at each level of a dimension, which number would you use?
A. the number of columns in a logical table
B. the number of levels in a dimension
C. the number of dimensions in a business model
D. The number of tables in a physical model
E. the number of distinct rows in physical column
Question is
what is the rule to set the number of elements at this level?
If its been set depending upon the rows in the table . what will happen if the rows gets added every hour ??
Edited by: ZSAM on Jun 8, 2011 7:06 AM
Edited by: ZSAM on Jun 8, 2011 8:22 AM

The ratio between the levels is what is important I believe. BI Server will use this information to determine which aggregate source to use. You should use the number of distinct rows as the value.
You can also right click the hieracny and use "Estimate Levels" to auto-populate the numbers for you.
Paul

Write two functions to find the the number of elements in a linked list?

I am trying to Write two functions to find the the number of elements in a linked list. One method using recursion and One method using a loop...
//The linked List class is Represented here.
public class lp {
public int first;
public lp rest;
public lp(int first1, lp rest1)
first = first1;
rest = rest1;
The program i wrote so far is
import java.util.*;
import linklist.lp;
public class listCount{
//loop function
public static void show_list(lp list)
int counter = 0;
while(list != null)
list = list.rest;
counter++;
System.out.println ("length computed with a loop:" + counter);
//recursive function
public static int recursive_count(lp list)
if (list.first == null)
return 0;
else
return recursive_count(list.rest) + 1;
//main method
public static void main (String args[])
lp list1 = new lp(1, new lp(2, new lp(3, null)));
show_list(list1);
System.out.println("length computed with a recursion:" +
recursive_count(list1));
at the if (list.first == null) line i get the error " incomparable types:
int and <nulltype>" I know this is a beginners error but please
help...What should I do?

byte, char, short, int, long, float, double, and boolean are primitives, not objects. They have no members, you cannot call methods on them, and they cannot be set to or compared with null.

Number of elements in target to host DMA FIFO

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