FPGA to HOST DMA

I am trying to record rising edge timestamps of a digital signal input to a spreadsheet using a CRIO. I have been getting some bad data elements recorded (although there are periods without faults). This is perhaps the input signal but i would be greatful if someone could check my VI's for any obvious mistakes.
I would also like to do the same with another input signal. Should i use 2 FIFOs, as below?
Many Thanks
Erny

ern,
Here are some thoughts.
Make sure that your FIFO type is Target to Host - DMA. If you use more than one, make sure that the DMA Channel is unique for each (0 and 1 for instance). Check the depth to make sure that you are not running out of space in the FIFO. Your FPGA code looks ok to me.
In the GUI, you are specifying to read 1023 elements at a time. Is your FIFO this same size? This means that you will most likely always miss edges as the GUI will not read out the data until 1023 data points are present. You are trying to stream edge timestamp information to the GUI so you have to stay ahead of the FPGA or you will miss data. You could code your GUI so that you use a shift register to pass the number of Elements Remaining back as an input to the read operation as the Number of Elements to read. You could seed the shift register with a value of 500 (or something like that) as the initial read. You would also have to make sure that if the number of elements remaining was too small (or zero) that you set it to some minimum or you may read data out one point at a time depending on your edge rate.
In you GUI loop, you are writing to a file too. You might want to use a producer consumer type architecture to read in the data. One thread would read out the fifo as you currently have. A second thread would write the data to a file. You would pass data from the fifo thread to the file writer thread with a queue.
Hope this helps!
-cb

Similar Messages

FPGA target to host DMA transfer speed

Hello,
------------Task summary:
I'm currently working on a data acquisition-heavy project using a PXIe chassis system (plus a host computer), see below for the components.
PXIe-PCIe8388 x16 Gen 2 MXI-express (controller)*
PXIe-1082 (chassis)
PXIe-7966R (FPGA)
NI 5772 (AC version, IO Module)
*note: the controller is connected to a PCIe port on the host computer with the full x16 bandwidth.
For my application, I need to acquire a fixed number of samples (16000) from each channel of the IO module at a fixed sampling rate (800MS/s). Each acquisition will be externally triggered at a fixed frequency, 50kHz. The number of acquisitions will also be fixed. Right now I'm aiming for about 90000 acquisitions per session.
So in summary, for each acquisition session, I will need (16000 samples per acquisition) * (90000 acquisitions) * (2 AI channels) = 2.88e9 samples per acquisition session.
Since each sample is transferred as a 16-bit number, this equates to 5.76GB per acquisition session.
The total time per acquisition session is (90000 acquisitions) / (50kHz per acquisition) = 1.8 seconds.
--------------Problems:
I'm having problems transferring the acquired data from the FPGA to host. I think I'm seeing an overflow on the FPGA before the data is transferred to the host. I can go into more detail pending an answer to my questions below.
--------------Questions:
I want to ask a few general questions before posting any code screenshots. Assuming my math is correct and the host computer 'good' enough, is it theoretically possible to transfer data at my required throughput, 5.76GB/1.8seconds = 3.2GB/s using the hardware that I have?
If it is possible, I can post the FPGA and host VIs that I'm using. If not, I will have another set of problems!
Thanks,
Michael

thibber wrote:
Hi Michael,
I have a few questions / observations for you based on your post:
First, you mention that you are using the PXIe-PCIe8388 x16 Gen 2 MXI-express. This is only compatible with the NI RMC-8354, so when you mention the streaming speeds you are looking to acheive, is this streaming back to the RMC, or to something else? Is the NI RMC-8354 the host computer you are mentioning?
When it comes to streaming data with the NI 5772 and PXI 7966R, there are a few different important data rates. First, the NI-5772 can acquire at a maximum rate of 1.6 GS/s with 12 bit resolution = 2.4 GB/s. This is only if you are using 1 channel, for 2 channels the rate is halved. Are you planning on using 2 separate 5772 and 7966Rs?
The 7966R can stream data at a maximum rate of 800 MB/s, so we have a data rate coming into the FlexRIO's FPGA (2.4GB/s) and going out of the FlexRIO's FPGA (.8 GB/s). The data that isn't being sent back to the host accumulates in the FPGA's DRAM. Lets say we have all of the FPGA's DRAM available to store this data (512 MB). Our effective accumulation rate is 2.4 - 0.8 = 1.6 GB/s, so our FPGA is going to fill up in about 1/3 s, streaming a total of 0.8+0.512 = ~1.3 GB back to the host before saturating and losing data.
There are a few options, therefore, to reach your requirement. One might be duplicating your setup to have more cards. 1.3 GB x 3 = 4GB, which meets your need. Also, the 7975R can stream data back to the host twice as fast and has 2GB of DRAM onboard, so you could store more data and stream faster, therefore meeting your requirement.
I hope that this information helps clarify what concerns come into play for this type of application. Please let me know if anything above is unclear or if you have further questions.
Thanks for replying. To answer your first question: I'm transferring to a desktop computer. The controller is able to connect with a PCI express x16 slot in the desktop computer. I'm not sure how to technically describe it, but the controller plugs into the PXIe chassis, then there is another card that plugs into the host computer's PCI express x16 slot, and finally there is a large cable that connects the card in the host computer and the controller.
For your second paragraph: the reason I used 16-bit numbers in my calculations is because that's how the data is handled in the FPGA after it has been acquired (assuming I keep it as an integer), is that correct? Then it's packed in chunks of 4 (one U64) before being inputted to the target to host FIFO (that's how the NI 5772 examples do it). Right now I'm only using one FPGA and I/O module, and I'm using both AI channels (I need to simultaneously sample two different inputs).
I might be able to live with half of the sampling rate, 400MS/s for both channels, if that means I will be able to acquire a larger amount of data. Getting another FPGA and IO module is also an appealing option. It depends on what my advisors think (I'm a graduate student), and if they want to buy another FPGA and IO module.
Questions:
I have a question about the 7966R vs the 7975R that you mentioned. I could probably find the information in the specifications, but I figured I would just ask you here. Is there any advantage to using the 7966R over the 7975R in terms of programmable logic elements? From what I could quickly read, the 7975R has more DSP slices and RAM, but does it have less general purpose logic blocks than the 7966R? The reason I'm asking is because the project that I'm working on will eventually involve implementing as much signal processing on the FPGA as possible. But obviously figuring out the acquisition part of the project is more important right now.
The other question I have is related to something nathand said in response to my first post. Is using multiple target to host FIFOs faster than using 1 target to host FIFO (assuming the combined sizes are equivalent)? I noticed that the FPGA has a max of 16 target to host FIFOs. Does each target to host FIFO reserve some amount of bandwidth? Or is the total bandwidth just divided by the amount of target to host FIFOs that I use in a given FPGA VI? Ex: If I only define 2 target to host FIFOs, each would have half of the total bandwidth, if I define 3 target to host FIFOs each would have 1/3, etc.
Hi Michael,
A few updates to my previous post:
First, I think I could have explained the sampling rate a bit more clearly. Using 2 channels instead of 1 means that each channel will have half the sampling rate (800 MS/s), but the total acquisition rate will still be the same (1.6 S/s).
There are some other options you might want to look into as well regarding your acquisition. For instance, is it acceptable to use only the 8 most significant or least significant bits of your measurement? Or to discard a section of your acquisition that is irrelevant to the measurement?
Also, if you do end up wanting to look in the direction of a 7975R, you would also want to likely switch to a 1085 chassis to fully utilize the improved streaming speeds. The 1082 has a limitation of 1 GB/s per slot, while the 1085 can achieve up to 4 GB/s per slot.
I look forward to hearing what other observations or concerns arise in your testing.
Andrew T.
National Instruments
I'll go ahead and respond to your latest response too. Thanks again for your help.
I think I understand the streaming rate concept. I'm not using time interleaved sampling. My application requires using the simultaneous sampling mode. I need two channels of input data.
Unfortunately I don't think I can sacrifice on bit depth. But for right now I can probably sacrifice half of the sampling rate, and reduce my acquisition duty cycle from 100% (constantly streaming) to 50% (acquiring only half of the time). My acquisition rate will still need to be 50kHz though. I'm planning to compromise on sampling rate by summing pairs of data points instead of simply decimating, and then transferring the data to the host.
Questions:
We (my advisors and I) think that the summing pairs approach would preserve more information than simply throwing away every other point. Also, we can avoid overflow because each 16-bit number only contains 12-bits of actual information. The 16-bit number will just need to be divided by 16 before summing because the 12-bits of information are placed in the 12 MSBs of the 16-bit number. Does that sound right?
As for upgrading the hardware, that would be something I would need to discuss with my advisors (like I said in my above response to your previous post). It would also depend on any exchange programs that NI may have. Is it possible to exchange current hardware for some discount on new hardware?

Number of elements in target to host DMA FIFO

Hi everyone,
I'd like to transfer a set of datapoints from a FPGA to a RT-host controller using a DMA fifo. If I use the "Get Number of Elements to Write" function on the FPGA target, do I get the total number of elements in both buffers, or just the one on the FPGA-target?
(see http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/)
Solved!
Go to Solution.

What type of data do you want to transfer over the FIFO? As in how many bits does each sample contain.
The reason I ask is because you can take a bit packing approach.
Lets take for example you want to take two samples of a measerment both samples are 32 bit and then send the data as a set to the processor.
If you just dump the data into a single FIFO you may lose track as to what was the rising edge, or falling edge data, or if the two samples you got from the FIFO are even from the same dataset.
To fix this use bit packing technique.
On the FPGA merge your two 32 bit data sets into one 64bit dataset.
Set your FIFO to 64 bits.
On the processor side of things all you need to do is read one 64bit dataset from the FIFO.
Use the split data to break the 64bit into two 32bit data fields.
Now you have your two data samples, and you can be garentee that it is from the same dataset.
If the sum of the data bits exceed 64 bits (the limit of the FPGA FIFO) then you will need to migrate to a more complex bit packing data schema where the data is split up among multiple 64bit datafields, with a defined bitfield header and identifier. For example the first 5 bits of the 64bit data identifies that this data block is 1 out of X data blocks, that when combinded together and reasembeled per the schema will represent your data..
I hope this helps.

How To transfer Data From FPGA to Host?

Hi, I am using Crio 9025 Other Input card for my project.
I am acquiring current input using 9203, and incoder input using 9411 differencial DI module.
I am getting encoder pulse count perfectally in both the direction.
Now What i have to do is. i want to store current input at each encoder pulse.
for example
Pulse number AI1       Al2
     1                30.50    30.89
     2                26.78    26.98
till last pulse.
1024                35.89    31.45
Thats It. Test Over.
What is the best why to do this.
CLAD
Labiew programmer

Hi Brijesh,
Kindly have a look at the NI example finder, I am sure you will find DMA or IRQ methods of data transfer.
Shreyas Hebbare
Shreyas Technologies
India

DMA from host to FPGA target is not supported for this remote system.

I am trying tocommunicate with my FPGA (on the cRIO 9002) from the RTOS. I setup up anOpen the correct VI reference with no error but as soon I try to access thefifo I receive error -63001 and the attached message says:
Error -63001 occurredat Open FPGA VI Reference in target - multi rate - variables - fileIO_old.vi
Possible reason(s):
NI-RIO FPGACommunications Framework: (Hex 0xFFFF09E7) DMA from host to FPGA targetis not supported for this remote system. Use another method for I/O or changethe controller associated with the FPGA target.
What other I/O optionsdo I have to move data asynchronously from the RTOS to the FPGA. I triedcreating memory but it appears that I can not write to the memory from the RTOSside.
We also have a 9012sitting around will using this cRIO instead solve this problem.
I am very very greenwhen it comes to LabView so I apologize if this is an easy question.
Solved!
Go to Solution.

As stated in the NI-RIO driver readme,
DMA is not supported from the host to the FPGA on the cRIO-900x series.
The cRIO-901x controller supports DMA transfers from host to FPGA and
FPGA to host while the cRIO-900x series controllers only support FPGA
to host DMA transfers. Therefore, LabVIEW returns an error if you try
to transfer using DMA from the cRIO-900x controller.
The 9012 looks like the ideal solution, you are very lucky to be having extra hardware laying around
Rob K
Measurements Mechanical Engineer (C-Series, USB X-Series)
National Instruments
CompactRIO Developers Guide
CompactRIO Out of the Box Video

Passing data from RT host to FPGA through DMA FIFO

Hello,
I am trying to write some data from an RT host to FPGA target using DMA FIFO then process this data and then read them back from the FPGA target to the RT host through another DMA FIFO. I am working on NI PXIe chassis 1062Q, with NI PXIe-8130 embedded RT controller and NI PXIe-7965R FPGA target.
The problem I am facing is that I want to send three different arrays, two of the same size and the third one with different size, and I need the smaller one to be sent to the FPGA first. I tried using flat sequece with two frames in the FPGA VI. In the first frame I read and write the first array in a while loop which is finite (i.e., finite number of iterations). The second frame contains the process of reading and writing the second two arrays (of the same size) in a while loop that can be finite or infinite (according to a control). The problem is that this didn't work. The 2 arrays are displayed on the front panel of the RT host VI and are working fine, however, the array that should have been read in the first sequence doesn't show up on the front panel of the RT host VI. This doesn't make sense because if it is not passed from the host to the fpga and vice versa then the second frame shouldn't have been executed. Note that I am wiring (-1) to the timeout to block the while loop iterations till the passing of each element is complete. Thus the first while loop has 3 iterations only. Could someone help me undersdtand why this happens and how to solve this problem?
I am attaching a picture of both the host and the fpga vi.
Thank you.
Solved!
Go to Solution.
Attachments:
RT host vi.png ‏102 KB
FPGA vi.png ‏28 KB

No need to initalize the arrays with values that you will immediately overwrite. Here's what I believe to be equivalent code:
The array outputs should be wired directly to the FPGA FIFO writes. Do not use local variables when you can wire directly.
If you know that you want to transfer the Temp Data Array first, why not make your code do that? Eliminate the sequence structure, and put the functions in the order in which you want them to execute. Use the FPGA reference and error wires to enforce that order. You might consider writing the Temp Data Array, reading it back, then writing the Real and Imag A arrays, to see if that gets you the results you expect. Run the code in simulation (in the project, right-click on the FPGA target and execute on the host with simulated IO) so that you can use execution highlighting and probes to see what is happening. Wire the error wires through and see if you get an error anywhere. Make sure you're not missing something simple like looking at the wrong starting array index.

How do I communicate data to a Host VI from an FPGA sub vi without ending the sub vi

I am trying to send timestamps of events that happen in my FPGA sub vi to be collected by the host vi on a windows computer in Labview 2010. The trick is that I do not what to stop any of the parallel loops in my sub vi from executing while I do this. Due to the amount of information collected, I am not sure it is feasible to create an array within the FPGA sub vi to store the data until the end of the trial. Does anyone know of a solution to this problem?

I'm not sure I understand correctly, but you can use a Target to Host DMA FIFO to transfer data from a FPGA VI to the Host VI.

Fpga DMA FIFO compilation error

Hello,
I have a cRIO 9074 with FPGA. I am trying a simple piece of code to learn how to aquire data that is generated on the FPGA at a rate of 10 KHz and transfer it to the Host VI for processing it later offline. However, I encounter this compilation error when compiling this basic FPGA VI containing a FIFO
write node (picture of the VI attached below). In the Compilation Report, it says that there were 256 Block RAMs used (the
total number is 40), therefore an error was produced. The exact compilation error
notification from the Xilinx report is reproduced below:
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow -timing toplevel_gen.ngd
toplevel_gen.pcf
Using target part "3s2000fg456-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
ERRORack:2310 - Too many comps of type "RAMB16" found to fit
this device.
ERROR:Map:115 - The design is too large to fit the device. Please check the Design Summary section to
see which resource requirement for your design exceeds the resources available
in the device. Note that the number of slices reported may not be reflected
accurately as their packing might not have been completed.
NOTE: An NCD file will still be
generated to allow you to examine the mapped design. This file is intended for evaluation use only,
and will not process successfully through PAR.
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
Number of errors : 2
Number of warnings : 125
ERROR:Xflow - Program map returned error code 2. Aborting flow
execution...
Bitstream Not Created
Timing Analysis Passed
What does this mean? How can I fix this error?
Thank you,
Bogdan
Solved!
Go to Solution.
Attachments:
FPGA.png ‏16 KB

Sorry, I forgot to mention that...LAbVIEW 2009. And yes, this is the only loop on the FPGA.vi. I just made up this code to understand how exactly I would save some data on the host for subsequent processing, but I didn't get to that point because the VI on the FPGA does not compile successfully. Do you know of any example of the most basic code for DMA FIFOs between the FPGA and Host Computer? This should be pretty straight forward, but for some reason it's not.
Thanks,
Bogdan

Flexrio FPGA dma and dram simulation

I have a pair of Flex RIO 7966r boards where I am trying to perform DRAM to DMA transfers. Each FPGA uses both banks of DRAM. One bank for capturing Camera Link frames, the other bank for capturing sub-frames from within each frame (And performing some processing on the sub-frame data).
Each DRAM bank is written into from their own target scopes FIFOs.
Each DRAM bank is read into their own target-to-host DMA FIFOs.
When only one side is operating or the other (Capturing sub-frames by themselves or full frames by themselves) everything flows nicely. But when I capture both at the same time, there appears to be some sort of contention in the DRAM (I suspect from the DMA engine). Since I am simulating all of this, I would like to ask if anyone has the detailed descriptions of the DRAM interface signals below? These are generated by LabView but I have found no explanation of what they mean in any documentation.
Also, in the simulation build, there is obviously a DMA simulation. But from within the simulator, I can find no signals related to the FPGA based DMA FIFOs or the simulated DMA transfers. All I can infer about the DMA transfers is the effect on the DRAM above. The DMA FIFO is being populated directly from the DRAM (Yes, this is a highly modified variant of the 10 tap cameralink (with DRAM) example from the NI-1483 examples).
Does anyone know how I can see the DMA bahavior from within a simulation? This would most likely allow me to see exactly why the contention is taking place.
Thanks!

Hey xl600,
I'm not immediately sure how to have ISim display the DMA Engine behavior, but I'll see if I can I dig anything up for you. I've come across a couple of other users encountering issues with FIFO signals appearing in ISim over on the Xilinx forums, so it might be worthwhile to post there as well in case it happens to be due to ISim itself.
Regards,
Ryan

Strange FPGA FIFO DMA behaviour

Hi all,
let me warn that 1) the post is long, and 2) I'm conscious that the problem I'm having has many workarounds (some I know, some I don't, some I think to know...). However, I woul like to understand exactly why it's happening, both to be able to find the most efficient solution and for personal "culture"...
So, I have a very simple VI running on an FPGA: at each cyle, it reads 8 ADC channels and build an an array of 9 elements (time+8 channels). I'll refer to one fo this 9-element array as a "data vector". Because I have to pass this data vector to the host VI, I set up a DMA FIFO in which I write the elements in order: time, ch0, ch2 ... ch7, time, ch0, ch2... etc (I can't directly wirte arrays in the DMA FIFO).
The host VI opens a reference to the fpga VI, invokes the start method and then enters a timed loop. On the first iteration it attempts to read 0 elements, obtaining the info on how many elements remain in the FIFO. Then using a feedback node it passes this information (N) to the next cycle, in which it reads K = 9*floor(N/9) elements (i.e., a integer number of data vectors) and reshape them in a Kx9 array. Finally, it formats the array and write it to a text file. Then the cycle repeats using the number of remaining element obtained from the previous iteration.
Now, the problem is that in the host VI the user has the ability ot set both the sampling frequency of the FPGA and the timed loop frequency. While this allows to find the preferred match of sampling frequency and wiriting (to file) interval, it may happen that the values are such that the FIFO saturates (i.e. the timed loop that empties the FIFO executes too slowly compared to the FPGA acquisition that fills it), and this has two main consequences. One is loss of data, that I don't care in this case as long as I notify the user that he is loosing data. The other one is that, even when i set the parameters back to a combination that allows the buffer not to be filled, I've lost trace of the "first element" of my data vector.
Now, I thought I had an explanation for that: when the buffer saturates, the "FIFO write" in the FPGA code will keep timing out untill the buffer is (at least partially) freed, that can happen in any moment of its cycle. Let's suppose that it found the FIFO full when it was trying to write ch3, and then resumed (because it found free space in the FIFO) when trying to write ch0: this would result in an incorrect sequence of data (time, ch0, ch1, ch2, ch0, ch1, ch2, ch3...) that would compromise any subsequent reading.
However, I'm observing another behaviour on another routine that makes me doubt about this explanation. (I told you the post was long!).
So, actually (I layed you before...) the FPGA code is writing two identical FIFO (FIFO2), not just one. This is because I want onether routine to run and visualize data independently from the one that writes them to file. This "visualization routine" opens a reference to the FPGA code, doesn't invoke the start methode and enters a loop that is almost identical to the one of the host VI, except that it sends the shaped array to some graph and similar instead of writing it to file. Now, because this routine is meant to be run as the user needs to watch the data, it often happens that it is started with big delay with respect to the FPGA code, resulting in FIFO2 being full. Thus, as expected, the reconstructed array is screwed up because the first element is no more what it is expected to be. However, stopping and restarting this rountine whithin an interval shorter than the time needed to fill the FIFO2 buffer (that is only possible if the sampling frequency is relatively slow, as stopping and restarting a routine takes at least a couple of seconds) makes it work. This doesn't match to what I would expect from my previous explanation, because stopping this rountine doesn't stop the FPGA code (i don't want to) and doesn't reset the FIFO2 buffer, so if there is a shift in the order of the elements from a previous timout, it should be maintaned...
Understanting why this is happening is interesting to me not only because it demontrates that I don't really understand how this FIFO thing works, but also because it would probably suggest me a simple solution to implement in both routines when I detect a write timeout from the FOGA code.
Does all this make sense to you?
Thanks
Giacomo

I had some time today and I thought this was an interesting question so based on your description I went ahead and created a LabVIEW project template of how I would implement this application. I used one DMA FIFO in a producer loop on the host then use queues to send the data to two seperate consumer queues. Check out the atachment and let me know what you think.
FPGA VI
Host VI
-Hunter
Attachments:
FIFO Example Program.zip ‏127 KB

Labview 8.0 FPGA DMA question

I am developing a control system which needs to access a big mass of
variable data (32 Mbyte) that i can put into the host computer RAM. In
labview tutorial and also on other web resources it is well described
how the DMA FIFO can be used to "write to" host PC memory (RAM) but
nothing about "reading from" the PC RAM. Is it possible? And which is
the control to be used? Do I need some lower level coding?
Thanx
Davide

Hi Davide,
As of right now, the DMA transfers are one-way only (FPGA to host).
Best regards,
David H.
Systems Engineer
National Instruments

Transfering signal from Host to FPGA

Hi:
I am new to labview FPGA. I am trying to set
up a transmitter by using Ni 5640r for my project.
Right now i can only generate OFDM signal from labview itself.
After that I try to program FPGA but when I use oscilloscope to catch the
signal, I failed.
I think I may have trouble on transfering signal from Host to FPGA.
Can somebody help me with that problem?
Thanks
Austin
Attachments:
PCP-OFDM.zip ‏1785 KB

Hello,
If you want to transfer data from the host to the FPGA you need to create a FIFO with the type set to ‘Host to Target – DMA’. When you then use it in the FPGA VI the only selection you can do is to read it. When you set the type to ‘Target to Host- DMA’ you can only write to it.
Regards,
Jimmie Adolph
Systems Engineer Manager, National Instruments Northern Region
Bring Me The Horizon - Sempiternal

How to decide the maximum number of elements for DMA FIFO in R series FPGA

Greetings!
I'm working on a project with NI R series PCIe-7842R FPGA board. To achieve fast data transfer I'm using target-to-host DMA FIFO. And to minimize the overhead, I'd like to make the FIFO size as large as possible. According to the manual, 7842R has 1728 kb (216KB) embedded block RAM, i.e., 108,000 I16 type FIFO elements available in theory (1728,000/16). However the FPGA had compilation error when I requested such amount of elements. I checked the manual and searched online but couldn't find the reason. Can anyone please explain? And in general, what's the max FIFO size given the size of the block RAM?
Thanks!

Hey iron_curtain,
You are correct that moving larger blocks of data can lead to more efficient utilization of the bus, but that's almost certainly not the most important factor here. Assuming of course that the FIFO on the FPGA is big enough to avoid overflows, I'd expect the dominant factor to be the size of read performed on the host. In general, larger reads on the host lead to improved throughput, up to the speed of the bus. This is because FIFO.Read is a relatively expensive software operation, so it's advantageous to make fewer calls to get the same amount of data.
Note that the larger your call to FIFO.Read the larger the host buffer needs to be. Depending on your application, it might need to be several times larger than the read size. You can set the buffer size with the FIFO.Configure node.
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/ explains the various buffers involved. It's important to note that the DMA Engine moves data asynchronously from the read/write nodes on the host and fpga.
Let me know if you have any questions about any of this.
Sebastian

DMA RT to FPGA guaranteed order?

I have a question regarding the sending of data via FIFO to an FPGA card via DMA. I would assume that if I have several locations in my RT code sending data via DMA FIFO that it is still guaranteed that any given DMA Transfer (let's say 12 data values) are delivered atomically. That is to say that each DMA node data is sent as a contiguous block.
Take the following example. I have two DMA FIFO nodes in parallel. I don't know which is going to be executed first, and they will most of the time be vying for bandwidth. Both nodes send over the SAME DMA FIFO. Does the data arrive interleaved, or is each sent block guaranteed to be contiguous ont he receiving end. Do I end up with
Data0 (Faster node)
Data1 (Faster node)
Data2 (Faster node)
Data3 (Faster node)
Data11 (Faster node)
Data0 (Slower node)
Data1 (Slower node)
Data11 (Slower node)
or do the individual items get interleaved.
I'm kind of assuming that they remain in a contiguous block which I'm also hoping for because I want to abuse the DMA FIFO as a built-in timing source for a specific functionality I require on my FPGA board. I can then use the RT-FPGA DMA Buffer to queue up my commands and still have them execute in perfect determinism (Until the end of the data in my single DMA transfer of course).
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Woah, new avatar. Confusing!
I am going to preface this by saying that I am making assumptions, and in no way is this a definitive answer. In general, I have always had to do FPGA to RT streaming through a FIFO and not the other way around.
When writing to the FPGA from the RT, does the FIFO.write method accept an array of data as the input? I'm assuming it does. If so, I'd then make the assumption that the node is blocking (like most everything else in LabVIEW). in which case the data would all be queued up contiguously. Interleaving would imply that two parallel writes would have to know about each other, and the program would wait for both writes to execute so that it could interleave the data. That doesn't seem possible (or if it was, this would be an awful design decision because what if one of the writes never executed).
Of course, this is all assuming that I am understanding what you are asking.
You're probably safe assuming the blocks are contigous. Can you test this by simulating the FPGA? If your'e really worried about interleaving, could you just wrap the FIFO.write method up in a subVI, that way you are 100% sure of the blocking?
Edit: Had a thought after I posted, how can you guarantee the order things are written to the FIFO? For example, what if the "slow" write actually executes first? Then your commands, while contiguous, will be "slower node" 1-12 then "faster node" 1-12. It seems to me you would have to serialize the two to ensure anything.
Sorry if I'm not fully understanding your question.
CLA, LabVIEW Versions 2010-2013

Data transfer from RT to FPGA using DMA FIFO

Hello all,
My question is "How do you stream data from RT target to FPGA target using DMA FIFOs?"
I would like to control some indicators (or controls) in FPGA vi using controls in the RT vi using DMA FIFO.
I have used four controls in my RT vi, but I get only one indicator out on my FPGA vi. (I would actually like to use some controls on the FPGA target using controls on the RT target)
Is this possible?
Can anyone help me with this?
I have attached my vi s.
Attachments:
fpgatest.vi ‏28 KB
rt_test.vi ‏73 KB

Based purely on your example, I see two options:
1. Do as RavensFan suggests and use Boolean Array To Number to send a single number down to the FPGA. Your FPGA can break up the number easily enough to update the indicators.
2. Just write dirctly to the indicators. I do not see a need for the DMA. Again, based purely on your example.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines

FPGA to HOST DMA

Similar Messages

Maybe you are looking for