PID (FPGA) Gain Values

Hi folks,
i´m using a PID-Module on the FPGA level.
Now i want to get the system stabil. Usually the I-gain is a very small value (i.g. 0.005). But you get 1,2,3,...
With the P-Gain is everything ok. It´s working.
If i increase the I-Gain, the system is freaking out. So, i need smaller values.
And the D-Gain has no influence of the system at all.
Well, i know that the the FPGA system doesn´t accept fluent point values.
From my point of view i must change something in the default option.
But i dont know exactly what and which values i have to change.
Do anybody have an idea what to do?
Thanks a lot
Andi

I have the same problem as you. In my case I think that the trouble is the sampling time (25ns) that is so small that almost any valour of the Ki constant make the system trip, and also because of that the derivative time is useless (also you can check to use 1/Ti, there are different ways of considering the PID constants).
I started using other PID VI, I get it on a sample from NI (CRIO motor control, altough you don´t have a CRIO you can use that PID VI, it´s more complete). Maybe you have the same problems at the beggining with it, but you can change the values of the constant Ilim (this is the antiwindup value for the Ki constant) and things get much more better just with Ki=1. Things worked that way but I don´t really liked it.
I finally decided to use my own PID algorithm, I´m still working on it, and by now I have the same troubles, but in the future I will scale the Ki, Kc and Td inside the FPGA module and decrease the PID sampling frecuency and hope everything starts to work fine at last.
Best regards.

Similar Messages

PID FPGA

Bonjour à tous,
Devant développer une régulation numérique en PID, je m'était inspiré d'un exemple de PID FPGA se trouvant dans LabVIEW pour développer mes programme RT et FPGA que vous trouverez en piece jointe.
Ayant finis la premiere partie de développement pour pouvoir tester le PID simplement sur mon système, je suis passé aux tests.
J'ai commencé par agir sur le coefficient proportionnel pour asservir le procédé, jusque là rien de bien compliqué. Une fois le gain proportionnel fixé, la suite logique est de fixé le gain intégrateur qui est sensé supprimé l'erreur statique qui pourrait resté. Mais là c'est le drame ! Cette partie ne fonctionne pas du tout et fais faire n'importe quoi au systéme.
Je voulais donc savoir si quelqu'un avait réussit a faire fonctionner ce PID et comment il avait fait.
Sinon est-ce que qu'un aurait une idée de comment je pourrais m'y prendre ?
Cordialement
Nathan
Pièces jointes :
PID.zip ‏401 KB

a couple of things. you are specifying 2 usec as loop rate but the module you are using for output is 10 usec.
you are specifying loop rate of 2 usec but your acquisition rate is specified as 20 usec.
the value of the calculated integrator coefficient is likely too small for the 16 bit PID calculation NI uses.
you will be better off coding your own PID algorithm modeled after the NI one.
Stu McFarlane
Viewpoint Systems, Inc.

PID (FPGA) - Convert 16bit output to 24 bit

Hello,
Im controlling a device in Closed Loop using the PID (FPGA) vi. The output of this is I16, but it would be nice if I could convert it to a I24, or I32. The output of this vi is sent to two different Analog Outs on my Op-Amp circuitry. The op-amps are set up as summing amps, so it would be ideal to send the lower 8 bits to the first AO (fine output), and the top 16 (15+sign) to the second AO (coarse output).
I haven't found an easy way to do this yet. So far, I've been thinking of just using the I16 output value, split it into two 8 bit numbers. The lower 8 bit controls my first AO. The upper 8 bits is combined with another 8 bit register that gets incremented everytime the 8-bit number becomes saturated, and controls the 2nd AO.
I've attached a pic to make it more clear (I hope?). If I should be doing this another way, please let me know.
Or maybe I need to be controlling this system with 2 parrallel PIDs? One controlling the coarse control, the other the fine. The feedback would be the same for both PIDs.

Hi bones,
even on FPGA you should be able to use "split numbers" and "join numbers" functions...
And you can use boolean operators on numbers. Like sign = I16 && 0x8000
That way you would get away from all those number TO boolean array TO cluster of booleans TO unbundle TO bundle TO boolean array TO number conversions (also called RubeGoldberg, search for this in the forum!).
Message Edited by GerdW on 12-07-2009 08:52 PM
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

7344 PID proportional gain = 1 but actuator still unstable.

Hi LabView Gurus,
Problem: With the 7344 PID P gain set to 1 (I & D to zero), I cant get correct performance from my Dynaserv servo drive using encoder feedback.
I'm driving a Dynaserv (ActuatorM1075B60 ControllerD1075B02) in torque mode with an NI PCI7344. All is working Ok, except that with a proportional gain of 1 the system is close to oscillation and overshoots when doing step velocity changes or position moves. It appears that the system requires a gain of less than 1 (with a gain of 3 or greater the actuator becomes unstable)
The controller is working in absolute position mode with encoder feedback. The Dynaserv encoder provides 425984 counts per revolution - which is much lager than I've seen before. I normally work with encoders that provide 2000 counts/rev and these work well with a wide range of PID params usable depending on the mechanical set-up.
I require the Dynaserv to operate at anywhere from zero to greater than one rotation per second with accurate step changes in velocity and position with less than 0.1 degrees or 100 counts of overshoot. I can't achieve this even with a gain of one currently. It would appear that the encoder is simply providing too many counts.
I've tried limiting the 7344's output both in software and using a voltage divider on the output, but this doesn't solve the problem - I can't reach full torque as the output is reduced. I've also looked into gearing and other settings on the 7344 but can't see anything helpful. Note also i have the Dynaserve controllers gain at the minimum setting also.
Any ideas? Your thoughts would be much appreciated!
Cheers,
Shane.

Shane,
I agree with your assumption, that the issue is caused by the high resolution of the encoder. If you increase the encoder resolution, this has exactly the same effect as increasing Kp.
So compared to a standard 2000 counts/rev encoder, your encoder scales Kp with a factor of about 213. As the 73xx boards run the PID loop on a DSP without floating point unit, this encoder eats up all the headroom for your Kp value.
From a functional point of view, such a high resolution encoder rarely makes sense, as all the mechanical positioning errors of your system are typically much higher than the resolution of the encoder, so it doesn't add real accuracy to your system. In fact it may even add more issues if you want to run the motor at higher velocities, as thie means very high frequencies that need to pass the encoder cable. The 7344 supports up to 20 MHz encoder input signals, but at these frequencies cable damping and noise can become serious problems.
So if possible I recommend to exchange the encoder with a lower resolution version. By the way, is this a real quadrature encoder or are you using an emulated encoder signal, that is generated by your drive (typical setup for BLDC motors). In this case you may be able to reduce the resolution in the drive's configuration.
Kind regards,
Jochen Klier
National Instruments

Configuring the PID (FPGA) Express VI

Hello,
I'm implementing a control system using the PID (FPGA) Express VI. I was wondering if crucial to provide the correct sampling time: Does the Express VI's functionality depend on it, or is it only for calculating the initial quantized gains?

Hi there, The sampling time directly affects the integral and the derivative gain (see the formula at the details section over here). Unless you are doing a proportional control (only) I don't see a problem. For more reference check this other link.
Alejandro | Academic Program Engineer | National Instruments

SVT Gain & Phase - no gain value output

Our application has been using the SVT Gain & Phase.vi from the Sound and Vibration Toolkit
add-on for Labview with no problems until we try to upgrade.
The original versions in use are: Labview 8.2, Testand 3.5 and the Sound & Vibration Toolkit 4.0.
Basically, the SVT Gain & Phase.vi is used to return a gain value back into Teststand.
I ran our application using Labview 2009 and the
Sound & Vibration Toolkit 2009, a test based on the SVT Gain & Phase.vi failed.
Stepping through the code showed that the VI was not returning a dB gain value, but "Nan" instead.
Also the function would generate an error, details are:
Error code: -1945
Basic detail: The fundemental tone was not detected.
I also tried our application with Labview 8.6 and
Sound & Vibration Toolkit 7.0, this also produced the same problem.
When I looked closely at the other output values of the VI, detected frequency
and amplitude of the signals, these values were comparable with all previous passed
tests, despite the error with the gain value.
In fact, because the detected amplitudes of the signals were correct,
I was able to manually calculate the gain value even though the VI couldn't.
On one hand the function is correct to complain about one of the input signals
because it's not perfect, but why should the VI from an earlier version of
the SVT not generate an error ? Is the newer VI version less tolerant ?
Thanks,
Gary.

Dominic,
Thank you for your reply.
With reference to your question about the phase, it's something I cannot answer at this
moment as the phase value is not something we monitor.
Looking closely at how we are using the SVT Gain & Phase.vi, I realised there is scope
to improve the response signal y [EUy] value that is passed in.
By increasing the number of samples obtained from the output of the unit under test by
10 x, this gives a waveform with which the VI is happy to "detect the fundamental tone".
And so the gain value is returned as a number and not "Nan".
For the time being it's the solution we are happy with.
regards,
Gary.

Where is the PID (FPGA) Express VI?

I have LabVIEW 2013 RT and LabVIEW FPGA installed on my Windows 7 machine. Which palette is the PID (FPGA) Express VI on? I have looked on both the RT and the FPGA palettes. I have looked for the example C:\Program Files (x86)\National Instruments\LabVIEW 2013\examples\control\PID\fpga llb\CompactRIO. The example is not on my machine.

I don't have an FPGA Math & Analysis -> Control on 2012 or 2013. Maybe I failed to load everything I need. Here is my palette.

Does PID loop transfer values to new instance

Greetings Everyone,
I'm a new forum user, but I've been using Labview for about three years now.
I have an application that uses PID VIs in multiple cases of a case structure. Each case structure passes a different set of setpoints, gain schedules, limits, ect to the new instance of the PIDvi. What I'm wondering is this: When I switch cases to the new case structure, does all the integral and derivative information get lost in the shift registers of the old PID instance, or does labview keep them in memory and pass them to the new instance? If it kept it in memory it would be a great help, becasue there would be less upset in my PID loop. If not, then I'm going to have to pass a cluster of that information into the new instance...which I'd rather not do to save on system requirements (real time system).
Thanks for the input
Grub
Hell, there are no rules here...we're trying to accomplish something!!! - Thomas Edison

Using the shift register will only work if you make the VIs not reentrant. In any other case, you will need some means of global data storage. I think the most memory efficient is LV2 Globals (also known as Functional Globals), but I haven't tested it, and I know of some benchmarks that showed that the fastest is single element queues globals.
A single element queue global is a queue with the size of 1 where you always remove the element from the queue when doing an operation. This locks any other calls to the queue, because it's empty, and they will have to wait until you place the element back in the queue.
You can search for the other terms to find some documentation about them.
Try to take over the world!

How do I specify if the PID object is direct or reverse acting?

I have a process that requires a reverse acting controller - eg if the PV is above the setpoint, I need to increase the controller output to lower the PV. Where in the PID object configuration do I specify this?

Pat,
I think - you can achieve a "reverse acting" PID controller by setting the Gain value negative. However, if you manipulate the PID parameters you should know what effect it will have on your system. If you want to be sure you should simulate the parameter before you apply them to the "real" world. In addition you could verify the -Gain setting with the formula (position/velocity control equations) given in the Lookout online help of the PID control object.
Hope this helps
Roland
PS: I always keep in mind what my control profssor told us once - "just a minus sign (sign change) in contol theory could mean a lot"

PID query

hello,
I am new to PID programming and I had a dumb question. I am trying to control a valve such that I can control the pressure downstream of the valve. My input and setpoint variable are the pressure transducer measurement. However my PID should output a 0-5VDC signal to the valve which will in turn control the pressure downstream. Can this be done using PID controls toolkit. If yes then perhaps some nudge in the right direction would be awesome. I do not understand the output part which goes from -100 to 100. what is the physical significance of that? can that be directly applied to the valve actuator with simple math functions?
Thanks,
Vickey
Solved!
Go to Solution.

Hi Vickey,
I am not an expert in PID control and the attached VI is just a simplified example of the actual code, but it worked very good for us.
We were controlling a proportional valve and the set point was in % of the full scale range of the valve. In your case the 'output range' cluster can use something like 0 to 5 (volt). Maybe even something different, for example 1 to 5, so that you prevent the valve from fully closing the line, but this really depends on the application.
The PID gains values are the tricky part. In your case the values maybe totally different. I think out Ti was 0.01 instead of the 0.001 you see in the screenshot. I am not sure, but anyway you have to figure out what will work in your case.
Nick
Attachments:
valve_pid.vi ‏9 KB

PID autotuning

Hello,
I am not able to obtain new PID gain values in the PID autotuning wizard. It is showing NaN for Kp, Ti and Td. I am attaching my labVIEW file here. Please help.
thank you in advance.
Attachments:
PID_tuning1.vi ‏128 KB

Hi Arun
Thanx for the reply, If I use the Autotuning.vi I will have to use 1 vi for 1 closed loop, since am using 128 thermocouple in closed loop, that would mean i will need 128 PID loop. Is there any alternative solution?
Also am using the VI in RT, with out front end. so if I set autotune to "TRUE" the autotuning wizard will popup, which i dont want, so i guess i will remove that part of the functions. What do you suggest?
Thanx for the reply
Regards
Arun

Camera link protocol implementation on FPGA

Hi,
I want to configure the Basler camera parameters like exposure time, frame rate, Gain value etc. through 7966R FlexRIO & 1483 Camlink adapter module. But on FPGA there is no option to configure these parameters through .icd file or MAX. So I have to implement the Camera Link protocol in FPGA to configure these parameters of camera.
I found that camera link has 4 controls lines (CC1 to CC4) but I am not able to find how these lines works to control the parameters of camera. If anyone knows how these control lines work then please tell me or share any document to describe their operation. Or any other information through which I can implement the algorithm on FPGA to control the parameters of camera.
Any help will be appreciate
Regards

I ran into multiple issues with the Serial Server running through the 1483/7966. I was never able to reliably get the serial server to operate through the MAX NI Vision CLSerNat function. It seems the 1483 is just not well supported in Max in any way. This prevents the use of Pylon as your serial command/status tool. Those work great with other frame grabbers like the 1433, but the 1483 leaves you having to implement the entire capability yourself.
So, I wound up having to write my own serial driver for the BBPI protocol and message processors for the various standard message types the Basler ACE cameras respond to.
Though I can't provide code, if you need to write your own protocol stack and have questions on the Basler interface, I'm worked through many of the issues.
One issue you may encounter is with the serial server itself. It operates in byte mode. I was never able to understand the reasons, but between a VI running on a host PC interacting through the stock serial server running on an FPGA (7966) through a RT target (PXI-1082) byte mode inserted very large inter-character delays. Often so large as to cause the Basler camera to claim a timeout and terminate the command. I had to modify the serial server to operate in a one-shot FIFO mode for transmit data as follows:
In the FPGA serial_interface.vi (For non byte-mode)
Increase the FIFO to 64 bytes to accomodate the largest Basler message
Add a "Transmit now" control to trigger a full FIFO output
Add a "Transmit length" control to control the number of bytes transmitted
In the upper level serial_server.vi
Modify the transmit loops to better detect bytes to transmit from the Ethernet interface and to direct the transmit data to the new WriteBytes vi
In the FPGA_UART.llb library
Add an FPGA_UART_WriteBytes.vi to handle the non byte-mode modification and to 'chunk' up transmit data into 64 byte (max) pieces. In the BBPI and Basler protocols, this has not been seen since all the messages are small.
With these modifications, I could then write a state machine to handle the basler BBPI protocol. States I chose for this were:
Idle
When a command is queued, it is fed to the serial server in its entirety. The serial interface sends it to the camera as a complete message with no inter-character gaps)
Wait for ACK
Every command must have an ACK/NACK
Go back to idle if sending a write or command message
Wait for BFS (Only if sending a read request)
Wait for FTF
Wait for the data lengthbyte
Wait for BFE (Goes back to idle once all bytes received)
It's up to you if you want to handle the checksum capability of the BBPI protocol. It's surprisingly tricky. I hsould have saved myself the headache and just worked entirely in non-checksumming mode.
Once I got that all working, I could then write message handlers for each of the basic Basler message types:
Enum
String
Bitfield
Scalar
etc..
followed by specific message handlers for each of the messages I wanted to deal with. My usual technique is to perform a mass serial configuration as soon as I fire up the FPGA. I haven't tried to use the trigger port signals (CC1 etc) but those can all be configured and controlled through the serial port once you get a message passing capability in place.

PID control to maintain constant heater electrical power?

Hi!
I am looking for a good solution for the following:
I have a heater wire (approx. 220 Ohms). I drive this wire with DC voltage. I measure the voltage drop on the wire, and the current running through it. I want to control not the temperature, but the calculated electrical power (P=U*I) in the range of 1mW to 1W.
Of course the resistivity is slightly different at different temperatures, so that is why I think I need active control.
Maybe someone could give me a good advice?
Thanks very much!

Hi,
Everything is set up for the hardware. I generate the DC voltage with a NI Static waveform card (DAQmx). I measure the voltage drop and the current (via voltage drop measurement on a calibrated resistor connected in serial with the heater wire) with a Keithley DVM via GPIB card. The SetPoint is the required electrical power, the ProcessVariable is the calculated power from the measured U and I. The output is the driving voltage between 0-3 DC Volts, what I amplify with a factor 5.8 with an amplifier connected to the heater wire.
I try to use the PID.vi from the PID toolkit (I already use PI(D) controls from LabView for other heater wires, where I have to control temperature, and they work very efficiently and perfectly) for this purpose.
So far I try to find the proper gain values. My sampling rate is low, approx. 8 seconds. First I tried only the P control (zeroing the I and D gains of the PID.vi), to find a stable oscillation range, so I could go on with the PID Autotune vi. But no luck so far. I think it is also a problem, that this system is not linear: the P is not a linear function of U. Can you suggest how to go on from here?
Thanks very much!

Trouble changing gain setting on SCXI-1122

Attempting to change module gain using MAX 3.0.1 or the SCXI_Set_Gain function of nidaq32.dll with LabVIEW 6.1 generally has no results. Occasionally a gain change through MAX is accepted if the SCXI Chassis is turned off and back on after the gain change is made. The SCXI-1122 module is in slot 1 of an SCXI-1000 chassis and is connected to a PCI-6031E card. Operating system is Windows XP. Any ideas as to what might be wrong?

Dear DTI1
Thank you for choosing National Instruments Support!
The SCXI 1122 does not allow you to choose the gain -- even though the documentation says "Programmatically Selectable". What this actually means is that when you specify a range to acquire, the NI-DAQmx driver will decide what gain to set.
You can however get access to this gain value by using property nodes. Hence, if your range is constant, the gain will remain the same, no matter where you try to change it.
Hope this helps!
Thanks and Regards
Shekhar S
National Instruments

How can I reduce FPGA compiler time

Hi,
I am trying to implement a PID control loop on the FPGA of a cRIO.
The VI which runs on the FPGA target takes very long to compile (1h+).
Does anyone have an idea while the compilation takes so long and how I might be able to inprove compilation time?
The program can be found in attachment.
Best regards,
Jasper
Attachments:
PID FPGA TEST.zip ‏160 KB

Hi Jasper,
FPGA's normally take a very long time to compile compared to software compilations. 1 hour sounds about right for a slightly above average sized project. Compile times of anywhere from 2-4 hours (and longer for larger devices!) are not unheard of.
Companies who are serious about FPGA compilation and rely on quick turnaround invest in servers which contain many computers to work on the compilation (this is also why when you compile, it asks you if you would like to compile on the "local sever" (your computer) or an external server).
NI also has a cloud compiler available that will let you compile your code on their servers, however you must pay for the time. I think they offer a free trial if you wanted to see how it works.
So if you seriously need quick turnaround, you must consider some serious hardware.
Otherwise, you will have to queue up multiple compilations and let them run overnight like the rest of us.
www.movimed.com - Custom Imaging Solutions

PID (FPGA) Gain Values

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