PXI 7833R pull up

I am using Labview FPGA and PXI 7833R card.
the PXI 7833R card has normal output swing from 0 to 3.3v. If I wanna drive a 5V CMOS logic . The manual says I can use a pull up resistor.
My question is that when I use the pull up resistor, should I set up the digital output through the FPGA software, or I just use a pull up resistor without doing anything else?
this picture is how the manual does.
Attachments:
c.jpg ‏32 KB

Hi There:
Thank you for your question. I am not sure I have understood your question correctly so if this post does not answer your question please let me know so that I can research further.
Basically all the pull up resistor is taking the output of 3.3V and pulling it up to 5V. The board outputs 3.3V when a high logic is seen at the terminal. The logic that you send out to the terminal is determined by the code in your FPGA vi. So to answer the question, you will have to connect a pull up resistor and set the digital outputs using the FPGA software which in this case is LabVIEW FPGA.
I hope that helps.
Best Regards,
Jaideep

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Guillermo,
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Hello jyang72211,
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Why does opening and closing FPGA references increase Windows XP handles by 3?

Hello.
We run a test system here that uses TestStand to communicate
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could be related to this known issue--
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Message Edited by Jeff Bohrer on 10-27-2009 02:21 PM
Jeff

Best way to synchronize multiple FPGAs

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Hi. Can anyone advise of a clean way to migrate or copy / paste my CLIP modules between FPGA targets, please? I've about 30 test rigs, each testig a different product. Each contains a PXI-7833R card. We had one fall over recently and I learned that the card is now obsolete. The PXI-7842R is touted as a drop-in replacement. I'm finding the software support for migrating in the project to the new FPGA somewhat cumbersome. I had hoped I could simply change the device type in FPGA target properties, but it appears that I can't change the FPGA target type; apparently the target device can only be set when the target is first created in the project. Normally, this wouldn't be a problem, since the contents of the old (7833) target can be copied and pasted into the new (7842) target within the project. However, my FPGAs are now using VHDL components and the CLIP properties cannot be copied / pasted: they need to be added and configured manually, which is quite labourious. Each of my pijects might have 10 CLIP modules to manually configure and I'm dreading it, but in order to minimise test rig downtime in the event of a failure, I wish to build each of these projects for the new PXI-7842R target hardware in advance of requiring it. Anything the community can suggest would be a help. Thanks.

It probably would have been a good idea to hit "Preview" before posting. This is a re-post, but much more pleasing to the eyes!!
Can anyone advise of a clean way to migrate or copy / paste my CLIP modules between FPGA targets, please?
I've about 30 test rigs, each testing a different product. Each contains a PXI-7833R card. We had one fall over recently and I learned that the card is now obsolete. The PXI-7842R is touted as a drop-in replacement. I'm finding the software support for migrating in the project to the new FPGA somewhat cumbersome.
I had hoped I could simply change the device type in FPGA target properties, but it appears that I can't change the FPGA target type; apparently the target device can only be set when the target is first created in the project. Normally, this wouldn't be a problem, since the contents of the old (7833) target can be copied and pasted into the new (7842) target within the project. However, my FPGAs are now using VHDL components and the CLIP properties cannot be copied / pasted: they need to be added and configured manually, which is quite labourious.
Each of my projects might have 10 CLIP modules to manually configure and I'm dreading it, but in order to minimise test rig downtime in the event of a failure, I wish to build each of these projects for the new PXI-7842R target hardware in advance of requiring it.
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Fpga code generation error after updating from 8.5.0 to 8.5.1

Hi All,
I have a FPGA-VI which was compiled in LV 8.5.0 without errors. After I updated to 8.5.1 the Code Generation stops, telling me the clock domain is not supported for write FPGA I/O node (see attachment). Also I attached a picture of a simplified FPGA-VI which brings up the same error.
I use a PXI-7833R connected to a cRIO-9151 R Series Expansion Chassis with a NI-9421 modul (8-ch DI, 24V) installed in it.
My original FPGA-Code has a theoretical maximum of 22MHz, so I can't change the clock domain to 40MHz.
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Uli
Solved!
Go to Solution.
Attachments:
ErrorMessage1.jpg ‏30 KB
FPGA-VI1.jpg ‏17 KB

Hi Ruhmann, hi Basset Hound,
thank you for your reply and giving me a better insight in things.
I started my VI with 40MHz clock domain. The Vi got bigger, some more logic here and some more code there. Finaly the compiler couldn't satisfy the timing any more. Instead of optimising the code, I reduced the clock domain.
Until your post I didn't realise I use CompactRIO I/O. Is There a difference to (let me call it) "direct R-Series I/O"?
I need the Expansion Chassis (Connector 1), the 9421 (8-ch DI) and 94?? (8-ch DO) to connect 24V logic to the FPGA. Additionally I have two SCB-68 (Connector 2+3) for 5V logic (DI, DO, A/B linear position measurement, pulse generation) and some analog input. All code in 1 VI, but distributed in 3 loops.
To change the clock domain back to 40MHz, I have to optimise my code . Well, the code is sloppy , so optimising is OK .
To tell the hole story:
After updating to 8.5.1, my first contact to NI was by phone. The engineer asked for the Code, the project and the hardware.
It took a while for me to put the information in an email. Meanwhile engineer the found a paper with the solution I
mentioned in my second post and send it to me, before looking at my code. The paper said someting about "tightend timing constraints",
"safe communication" and "multiple DMA target to host transfer". Not exactly what I was doing, but I reinstalled
RIO 2.3.1 and ... compile successful.
@ Basset:
The simple VI (picture) in my first post reproducese the issue exactly.
I'm not at work any more, so I can't provide the full code or the SRQ# until tuesday (holiday on monday ).
FYI I'm located in Germany, so I called the german NI support.
Uli

One control to 2 different DIO lines

Hi there:
I am using PXI 7833R card and Labview 8.0 for windows. FPGA 1.1 version.
I have a problem about the DIO. In a previous program I use one boolean number to control one PXI 7833R digital output line. Everything works. Then I want to use the same boolean number to control two different Digital output lines. I did not change anything else, Just add a Digital output line to the node A(the circled one is added). The program does not work any more.
I used the oscilloscope to measure the output and got the signal I want for both output!!!
Anybody knows why?
Message Edited by lightmiddle on 03-06-2006 04:57 PM
Attachments:
twodio.jpg ‏1042 KB

lightmiddle,
I am still confused as to what you mean by "the result is far away from what I expect". What is actually happening? In your previous post you said "I used the oscilloscope to measure the output and got the signal I want for both output!!!"
I am still not sure how you can be using the FPGA 1.1 module with LabVIEW 8, this should not work. To add multiple lines to one I/O node in LabVIEW 8 you can simply drag lower edge of the I/O node downward to create more lines. See the attached image. I would also take a look at the shipping examples for LabVIEW FPGA module.
Message Edited by Doug M on 03-09-2006 06:36 PM
Doug M
Applications Engineer
National Instruments
For those unfamiliar with NBC's The Office, my icon is NOT a picture of me
Attachments:
two DIO lines FPGA.JPG ‏39 KB

Damage carry over?

We have the following setup:
Chassis: PXI-1042
Controller: PXI-8105
Module: PXI-7833R
Breakout box: SCB-68
The break out box is used for the module, and we use the internal 5V that is on it. Accidentally, I think we shorted the 5V to groud, so it no longer supplies 5V We replaced the bad module with a good one, and the same thing happened. We did that a couple of times, and we ended up having 6 modules without the 5V. My co-worker was convinced that when the 1st module was shorted, it affect the controller and chassis too, so that when we inserted other modules into the bad chassis with bad controller, the modules are fired. Is that even possible? Should there be some sort of protection on it? I read that there is a resetable fuse. Howcome it doesn't work? Any ideas?
Kudos and Accepted as Solution are welcome!

jyang72211,
Does this happen regardless of which slot the module is in? What is being done with the module when you notice that the 5V line malfunctions? Does this happen as soon as it is inserted into the chassis? Also, make sure that you are not hot swapping modules into the chassis. In other words, make sure the chassis is off when inserting and removing modules.
Also, according to page 2-26/27 of the R series manual, the operation of the internal fuse differs based on the revision of the module. Older revisions have a self-resetting fuse while newer versions have a fuse that must be replaced by sending the device in for repair to NI. I've linked the manual below.
Multifunction RIO User Manual:
http://www.ni.com/pdf/manuals/370489g.pdf
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How to write an .fds file using Matlab

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Getting up to speed on FPGA

I have a PXI-7833R in a PXI-1042 chassis. I am new to FPGA, and I want to get up to speed. Can you help me with the following?
1. Are there any relating FPGA material that I can use?
2. I would like to play with my FPGA, but there is a production bit file in my FPGA. I don't want to mess it up. I want to
2a. make sure that the bit file that I have is identical to the production bit file of the fpga
2b. know if 2a is true, I can revert the FPGA back after I am done playing with it.
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Kudos and Accepted as Solution are welcome!

I have an answer to some of your questions, and I'll try to reply as best I can.
1 and 6) Search NI knowledge base. It's always a good place to start. Also, NI offers an FPGA class which I have taken and can say is definitely worht while. Whether you are using an FPGA card on PXI or using FPGA on cRIO, all the best practices generally remain the same. If you can code on one, you can code on the other. These best practices however do not generally line up with best LabVIEW practices, so make sure you have a fundamental understanding of LabVIEW first. You don't want to begin thinking that how you code FPGA is necessarily how you should code a PC app. You will see lots of flat sequence structures, miminal subVI use etc all to improve efficiency among other things.
2) I'm not sure what you mean by production bit file. If you have whatever bit file is on there, though, you can always revert back based on what bitfile you set the open FPGA reference function to use.
3) There is example FPGA code in the LabVIEW examples
4) Read some knowledgebase articles to get a general idea then come back with specific questions. In general the things I try to remember are any subVIs should be reentrant, and arrays are generally not used. Also, if you need to buffer data, use FIFOs not read/write controls. I see Read/write controls on this forum being used far too often for the collection of data. But if you do this, you have no buffering and you might as well use scan engine because your data acquisition rates are no limited by your RT processor and not the FPGA.
5) again, LabVIEW examples
Anyways, there you go.
CLA, LabVIEW Versions 2010-2013

PXI 7833R pull up

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