Question about LakeShore 325 Temp.Controller

Hi guys,
I'm using the LakeShore 325 Temperature Controller for some measures. And i got stucked with this problem: i need to divide the ramp by segments. Which means that the ramp will not start from 0 all time. My idea is to make 1 ramp divided at a maximum of 4 segments. For ex: 1st segment from 100K to 200K, 2nd ramp from 250K to 400K, etc..
The problem is that i can't find that option on the instrument driver. It only allows me to configure the ramp, which means, that i can insert it's rate and if i'm going to have a set point or not. And the other option that is on the instrument driver is the configuration of the setpoint, that only allows me to insert 1 setpoint. What should i do? I need 2 setpoints, 1 for the minimum temperature and 1 for max. temperature.
I can't use the PID control, and i'm attaching the drivers here with 1 sketch of my main VI.
Thanks in advance.
TN
Currently using LV 8.5
Attachments:
lake_shore_325.zip ‏744 KB
new_test.vi ‏56 KB

Dear Maholtz,
First of all, I invite you to create a new thread for each new question, and to lik related topics into this new thread.
Now, about the instrument driver, the readme file clearly indicates that it is designed for LabVIEW 8.0 or later. To get version of those VIs for LabVIEW 6.1, I think you have two options:
1. Downgrade the existing version of the instruments driver using "Save for previous version" option. You will need a version of LabVIEW 8.x to downgrade to LabVIEW 8.0, then LabVIEW 8.0 to downgrade it in LabVIEW 7.1, and so on. this option exposes you to code compatibility issues, if some of the functionnality used by the LV 8.0 driver are not avilable under previous versions of LabVIEW.
2. Ask LakeShore for an instrument driver that supports LabVIEW 6.1.
Hope this helps,
.mrLeft{float:left} .mrInfo{border-left:solid 1px #989898;font-size:x-small;color:#989898}
Mathieu R.  
  CTD - Certified TestStand Developer / Développeur TestStand Certifié  
  CLAD - Certified LabVIEW Associate Developer  

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            elsif (Inp(i) = '0') then
                Temp(i) := '0';
            end if;
       end loop;
    return Temp;
    end function str_to_stdlvec;
    -- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
    -- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
    -- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
    function FrmBits (Bits : integer) return integer is
    variable Temp : integer;
    begin
    if (Bits = 12) then
    Temp := 12;
    elsif (Bits = 14) then
    Temp := 16;
    elsif (Bits = 16) then
    Temp := 16;
    end if;
    return Temp;
    end function FrmBits;
    -- Word symmetry check
    -- A word (16-bit) is checked for bit pair symmetry
    -- Example: In one byte there are 16 possible symmetry positions.
    -- 00000000, 00000011, 00001100, 00001111,
    -- 00110000, 00110011, 00111100, 00111111,
    -- 11000000, 11000011, 11001100, 11001111,
    -- 11110000, 11110011, 11111100, 11111111,
    -- Bit_7=Bit_6, Bit_5=Bit_4, Bit_3=Bit_2, and Bit_1=Bit_0
    function SymChck (Inp: std_logic_vector) return std_logic is
    variable Temp : std_logic_vector ((Inp'left-1)/2 downto 0) := (others => '0');
    variable Sym : std_logic := '0';
    begin
    for n in (Inp'left-1)/2 downto 0 loop
    Temp(n) := Inp((n*2)+1) xor Inp(n*2);
    Sym := Temp(n) or Sym;
    end loop;
    assert false
    report CR & " Pattern XORed/ORed = " & stdlvec_to_str(Temp) & CR
    severity note;
    return Sym;
    end function SymChck;
    -- When a symmetric byte, bit pattern is found, make the requested pattern rotate
    -- by one bit to become a non-symmetric pattern.
    function BitShft(Inp: std_logic_vector; Wire: integer) return std_logic_vector is
    variable Temp : std_logic_vector (Inp'range):= (others => '0');
    begin
    -- Bit shift all bits.
    -- Example: 16-bit frame word = 11111111_00000000 or 00000000_11110000
    -- After shifting the word returned looks as: 11111110_00000001 and 00000000_01111000
    if (SymChck(Inp) = '0') then
    if (Wire = 1 ) then -- 1-wire, shift 15-bits
    for n in Inp'left downto 0 loop
    if (n /= 0) then
    Temp(n) := Inp(n-1);
    elsif (n = 0) then
    Temp(Temp'right) := Inp(Inp'left);
    end if;
    end loop;
    else -- (Wire = 2) -- 2-wire, shift 8-bits
    for n in (Inp'left-8) downto 0 loop
    if (n /= 0) then
    Temp(n) := Inp(n-1);
    elsif (n = 0) then
    Temp(Temp'right) := Inp(Inp'left-8);
    end if;
    end loop;
    end if;
    elsif (SymChck(Inp) = '1') then
    -- Don't do anything, return the word as it came in.
    Temp := Inp;
    end if;
    assert false
    report CR &
    " Pattern Shifted = " & stdlvec_to_str(Temp) & CR &
    " Comparator Value A = " & stdlvec_to_str(Temp(15 downto 8)) & CR &
    " Comparator Value B = " & stdlvec_to_str(Temp(7 downto 0)) & CR
    severity note;
    return Temp;
    end function BitShft;
    -- Bit swap operation:
    -- Bit n of the output string gets bit n-1 of the input. ex: out(7) <= In(6).
    -- Bit n-1 of the output string gets bit n of the input. ex: out(6) <= In(7).
    -- Bit n-2 of the output string gets bit n-3 of the input. ex: out(5) <= In(4).
    -- Bit n-3 of the output string gets bit n-2 of the input. ex: out(4) <= In(5).
    -- and etcetera....
    -- This: Bit_7, Bit_6, Bit_5, Bit_4, Bit_3, Bit_2, Bit_1, Bit_0.
    -- Results in: Bit_6, Bit_7, Bit-$, Bit_5, Bit_2, Bit_3, Bit_0, Bit_1.
    function BitSwap(Inp: std_logic_vector) return std_logic_vector is
    variable Temp : std_logic_vector (Inp'range);
    begin
    for n in (Inp'left-1)/2 downto 0 loop
    Temp((n*2)+1) := Inp(n*2);
    Temp(n*2) := Inp((n*2)+1);
    end loop;
    assert false
    report CR &
    " Pattern Bit Swapped = " & stdlvec_to_str(Temp) & CR &
    " Comparator Value C = " & stdlvec_to_str(Temp(15 downto 8)) & CR &
    " Comparator Value D = " & stdlvec_to_str(Temp(7 downto 0)) & CR
    severity note;
    return Temp;
    end function BitSwap;
    function TermOrNot (Term : integer) return boolean is
    begin
    if (Term = 0) then
    return FALSE;
    else
    return TRUE;
    end if;
    end TermOrNot;
    -- Constants
    -- Transform the pattern STRING into a std_logic_vector.
    constant IntPattern :
    std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := str_to_stdlvec(C_FrmPattern);
    -- Shift the pattern for one bit.
    constant IntPatternBitShifted :
    std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitShft(IntPattern, C_AdcWireInt);
    -- Bit swap the by one bit shifted pattern.
    constant IntPatternBitSwapped :
    std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitSwap(IntPatternBitShifted);
    -- Define the bytes for pattern comparison.
    constant IntPatternA : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
        IntPatternBitShifted(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);
    constant IntPatternB : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
        IntPatternBitShifted((FrmBits(C_AdcBits)/2)-1 downto 0);
    constant IntPatternC : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
        IntPatternBitSwapped(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);
    constant IntPatternD : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
        IntPatternBitSwapped((FrmBits(C_AdcBits)/2)-1 downto 0);
    The intPatternA, intPatternB, intPatternC and intPatternD are used as a trainning pattern for the frameclock. As I think, the training pattern should be C_FrmPattern(C_FrmPattern is "11110000"  when  adcbits  is 16 and the wire is 2). Why do you use intPatternA to intPatternD as the training pattern? 
     The AdcFrame.vhd is attached.
     

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