RFSA, SCOPE & FPGA

Hi,
I just found some examples available in Labview Modulation that can
perform BPSK demodulation, such as "MT RFSA PSK Demod" and "MT niScope PSK
Demod".
I'm wondering about the outcome difference of BPSK demodulation performed
by RFSA(NI 5660), niScope and Labview FPGA?
Thanks,
Yang

Hi Yang -
The Modulation Toolkit VIs are simply used for caculations on acquired data. As long as you feed them the right data, you'll get the desired output. How you acquire it is pretty much up to you, though. You can use either the RFSA driver or the 5660 driver. (Note that, even though the example program you mentioned is called "RFSA", it actually uses the NI-5660 driver. This driver is built from the Scope and Tuner drivers, as you can see when you open any of its VIs.) The RFSA driver is newer and much easier to program, as you can see from the drastically reduced complexity of its example programs.
I'm not sure what you mean by LVFPGA...can you explain how you would use that?
David Staab, CLA
Staff Systems Engineer
National Instruments

Similar Messages

Best way to transfer single point data between loops on FPGA

Hi,
    I used quite number of loops on FPGA and need to transfer single point datas between loops. Only the current value of data is needed so buffer is not necessary. I don't want use target scope FIFO since it require minimum 21 elements and I only need the current value. Is there other way other than local variables?
    Thanks for help!
    Regards,
   Tom

Hi Godel,
Since this discussion thread is over 3 years old, it would be better to start a new thread with your specific questions to get quicker help.
I did a bit of research on your question, and found this helpful White Paper (http://www.ni.com/white-paper/7727/en/) that discusses the resources used for components in LV FPGA code. For local variables (although it depends on hardware), it looks like it uses Flip-flops and LUTs.
As for using local variables with different clock rates, I found this KnowledgeBase article that might help shed some light on your question - some issues can arise from using them with more than one clock rate (http://digital.ni.com/public.nsf/allkb/C683585460E88508862570D1006B7434)
Hope this helps! Again, if you have follow-up questions, I would definitely recommend creating a new thread
Xavier
Applications Engineering Specialist
National Instruments

How to display scope plot in Labview GUI?

I am trying to figure out how to show TDS8000 scope output plot in LV GUI(?)
This maybe a two fold question.
1. I suppose it may be necessary to adjust the scope scale with appropriate level so that the plot will show enough details of information. (e.g., finding Max and Min points)
2. how to display scope plot in LV GUI?
It would be a great help if anyone can share an example VI.
Thanks,

Hi jjlee,
It shouldn't be that difficult of a task. Most instrument drivers have
a simple initialize VI, and then some type of waveform measurement VI.
You would connect these two VIs and then take the output from the
waveform measurement (may be waveform acquire or something like that)
to a graph or chart (depending on if you're outside of inside of a
loop). That should be all you need to do for the simplest form of this
application. You would, of course, want to handle errors and close the
connection to the device when you're done collecting the data.
Hope this is of some help,
Regards,
Matt S.
LabVIEW Integration Engineer with experience in LabVIEW Real-Time, LabVIEW FPGA, DAQ, Machine Vision, as well as C/C++. CLAD, working on CLD and CLA.

Build installer with NI-RFSA

Trying to build a LabVIEW 8.0.1 installer with
NI-RFSA 2.0.7 as one of the "additional installers". The installer builds fine, but when I run
the installer, I get "Fatal Error!! Required NIPathsDir property
LV85DIR is undefined" and the installer exits.
What,
exactly, needs to be included in an RFSA installer (e.g., the
documentation for NI-RFSA says it includes DAQmx, NI-SCOPE and MAX
already). Do I also need to include the LV 8.5 runtime engine?
JoeG
Joe Gerhardstein
Averna Test Systems
Certified LabVIEW Architect
http://www.averna.com
Attachments:
installererror.gif ‏2 KB

Figured it out. Some additional digging led to the use of the "setup.exe /log logfile.txt" command, which can be run from the command line (shell). This generates a log file which I used to find my problem.
See attached image.
In the Shortcuts section of my installer, I specified a subdirectory with the forward slash (/) instead of the normal windows backward slash (\).
NI: Please please please add this to your KB article on this problem. Also please please please consider flagging this error in the installer builder. There are many illegal characters for Windows that are well documented. I know this builder is probably cross-platform, but we know what the target platform is here!
Joe Gerhardstein
Averna Test Systems
Certified LabVIEW Architect
http://www.averna.com
Attachments:
slashslash.gif ‏12 KB

Flexrio FPGA dma and dram simulation

I have a pair of Flex RIO 7966r boards where I am trying to perform DRAM to DMA transfers. Each FPGA uses both banks of DRAM. One bank for capturing Camera Link frames, the other bank for capturing sub-frames from within each frame (And performing some processing on the sub-frame data).
Each DRAM bank is written into from their own target scopes FIFOs.
Each DRAM bank is read into their own target-to-host DMA FIFOs.
When only one side is operating or the other (Capturing sub-frames by themselves or full frames by themselves) everything flows nicely. But when I capture both at the same time, there appears to be some sort of contention in the DRAM (I suspect from the DMA engine). Since I am simulating all of this, I would like to ask if anyone has the detailed descriptions of the DRAM interface signals below? These are generated by LabView but I have found no explanation of what they mean in any documentation.
Also, in the simulation build, there is obviously a DMA simulation. But from within the simulator, I can find no signals related to the FPGA based DMA FIFOs or the simulated DMA transfers. All I can infer about the DMA transfers is the effect on the DRAM above. The DMA FIFO is being populated directly from the DRAM (Yes, this is a highly modified variant of the 10 tap cameralink (with DRAM) example from the NI-1483 examples).
Does anyone know how I can see the DMA bahavior from within a simulation? This would most likely allow me to see exactly why the contention is taking place.
Thanks!

Hey xl600,
I'm not immediately sure how to have ISim display the DMA Engine behavior, but I'll see if I can I dig anything up for you. I've come across a couple of other users encountering issues with FIFO signals appearing in ISim over on the Xilinx forums, so it might be worthwhile to post there as well in case it happens to be due to ISim itself.
Regards,
Ryan

[basic] the scope of motion control in LV

I am a very beginner in motor control part.
Very recently, some motor need to use some proper control board in control unit or PC.
If so, what is the scope of the motion control driver (library) in LabVIEW developement version?
Some restricted motor type?
What other instrument should I prepare to use the driver?
What's the difference between this type(PC or control board) and NI motion controller?
Any materials for beginner should be welcomed.

For getting started with NI Motion Control I recommend this website. Here you will find tutorials, webcasts, selection guides and much more.
In general NI Motion solutions are not limited to specific motor types or applications. Depending on your application requirements you can select between motion control plugin-boards or software defined systems based on real-time hardware and/or FPGA technology.
Please have a look at our web resources first and post any specific questions to the forum.
Thanks,
Jochen Klier
National Instruments

Configuration data download to FPGA was not successful.

I have designed a board with the Spartan 6 LX9 TQFP144 Package.
I am able to load a bitstream to the device with the digilent HS-2. However the fpga can not selfconfigure from
the attached SPI Flash.
Here is the console output from iMPACT:
GUI --- Auto connect to cable...
INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4
INFO:iMPACT - Digilent Plugin: found 1 device(s).
INFO:iMPACT - Digilent Plugin: opening device: "JtagHs2", SN:210249983579
INFO:iMPACT - Digilent Plugin: User Name: JtagHs2
INFO:iMPACT - Digilent Plugin: Product Name: Digilent JTAG-HS2
INFO:iMPACT - Digilent Plugin: Serial Number: 210249983579
INFO:iMPACT - Digilent Plugin: Product ID: 30900152
INFO:iMPACT - Digilent Plugin: Firmware Version: 0109
INFO:iMPACT - Digilent Plugin: JTAG Port Number: 0
INFO:iMPACT - Digilent Plugin: JTAG Clock Frequency: 10000000 Hz
Attempting to identify devices in the boundary-scan chain configuration...
INFO:iMPACT - Current time: 27.07.2015 16:19:26
PROGRESS_START - Starting Operation.
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc6slx9, Version : 2
INFO:iMPACT:1777 -
Reading C:/Xilinx/ISE/14.7/ISE_DS/ISE/spartan6/data/xc6slx9.bsd...
INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
done.
PROGRESS_END - End Operation.
Elapsed time = 0 sec.
Selected part: N25Q128
Unprotect sectors: FALSE
INFO:iMPACT - Current time: 27.07.2015 16:20:19
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations.
INFO:iMPACT - Downloading core file C:/Xilinx/ISE/14.7/ISE_DS/ISE/spartan6/data/xc6slx9_spi.cor.
'1': Downloading core...
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1100 1110 1100
INFO:iMPACT:2492 - '1': Completed downloading core to device.
'1': IDCODE is '20ba18' (in hex).
'1': ID Check passed.
'1': IDCODE is '20ba18' (in hex).
'1': ID Check passed.
'1': Erasing Device.
'1': Using Sector Erase.
'1': Programming Flash.
'1': Reading device contents...
done.
'1': Verification completed.
'1':Programming in x4 mode.
'1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
INFO:iMPACT - '1': Flash was not programmed successfully.
PROGRESS_END - End Operation.
Elapsed time = 78 sec.
If i read that correctly Data was written to the Flash but the fpga was not able to configure from that data.
Done-pin is connected to 3.3V via a 470 Ohms Resisor.
The Flash is a N25Q128A13ESE40G, Datasheet here: http://www.farnell.com/datasheets/1674445.pdf
I can perform a readback, checksum and an erase.
If i do a read device status this is the console output:
INFO:iMPACT - Current time: 27.07.2015 16:36:27
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': IDCODE is '20ba18' (in hex).
'1': ID Check passed.
'1': IDCODE is '20ba18' (in hex).
'1': ID Check passed.
'1': IDCODE is '20ba18' (in hex).
'1': ID Check passed.
INFO:iMPACT - '1': Reloading FPGA configuration data stored in flash...
INFO:iMPACT:182 - done.
On the Flash side I have pulled s# and Hold up to 3.3V with 100k Resistors.
Can someone help me to find the problem?

So does the FPGA try to read the SPI flash when it boots ?
out with scope, probe the clock and the data , see if you can see it streamig out when you boot.
If so, then one other thing I see wrong a few times is data path of the SPI, single bit or 4 bits of data.
you have to make certain the bit file was created in the same width as the fgpa is expecting,
In ISE I think its in Impact where you make the SPI flash file and specify this .

Synchronise NI-RFSG / NI-RFSA with NI-TCLK

Is it possible to synchronise NI-RFGS and NI-RFSA devices using the NI-TCLK library?
I have a PXI system with a PXIe-5672 waveform generator / upconverter and a PXI-5661 downconverter / digitizer. I would like to synchronise them so they start transmitting / recording at the same time. I believe in general the NI-TCLK library can be used to achieve this?
I can't wok out how to use it. The "niTCLK configure for homogenous trigger" vi takes an array of "sessions", however I don't have "RFSA Get Session Reference" or "RFSG Get Session Reference" functions.
Is it possible to use the NI-TCLK library with RFSA and RFSG? If so, how do you configure it?
Thanks in advance
David
Labview 8.0 / Windows XP

I have attemtpted to synchronise transmitter and receiver using the TCLK library and the RFSG get Fgen session / RFSA get Scope session vi's. Both RFSA and RFSG have been initialised and have no start trigger set, and neither have been started. Their session references have been wired to a niTCLK configure for homogenous triggers vi.
However when I run TCLK synchronise or TCLK initiate I get the following erors.
Is it possible to use niTCLK with the digitiser in DDC mode? When I do not synchronise the RFSA (so only the RFSG is connected to the TCLK configure and initiate) I do not get the errors, but obviousy the RFSG is only synchronising with itself
niTClk Initiate.vi:1<append>
Session index (starts at zero): 1
Error reported by the instrument driver: 
TClk synchronization is not currently supported with the DDC enabled.
Device: PXI1Slot5
Property: Min Sample Rate
Invalid Value: 1.0e6
Maximum Value: 100.0e6
Status Code: -214237
niTClk Synchronize.vi:1<append>
Session index (starts at zero): 1
Error reported by the instrument driver: 
TClk synchronization is not currently supported with the DDC enabled.
Device: PXI1Slot5
Property: Min Sample Rate
Invalid Value: 1.0e6
Maximum Value: 100.0e6
Status Code: -214237

NI-RFSA Soft panel with 5600 and 5124

We bought a PXI system, with the following HW:
RF:
NI 5600 downconverter
NI 5124 Oscilloscope card
With this I want to use the softpanel of the RFSA (spectrum analyser), but it seems this cannot work because i cannot choose the scope card.
This because i can only choose a number for the digitizer device and not a name. I tried giving the NI-5124 a number and not a name, but this doesn't seem to work.
Is there an other way to still be able to use the Soft Front RFSA with this digitizer card?
Regards
Joost van Heijenoort

Hi Joost,
The RFSA Demo Panel will not be supporting any new devices in the forseeable future. If new analyzers are released in teh future, they will surely ship with tools to enhance ease of use, but the Demo Panel will continue to support the PXI-5660 exclusively (5600+5620).
Can you provide more detail on the functionality you are interested in? I will help you achieve this via other software if possible, and in any case will work with you to ensure you are successful.
Regards,
Andy Hinde
National Instruments

How do you capture IQ data with RFSA vi's triggering from ext trg on digitizer?

I am trying to write an application using RFSA vis that will capture IQ data when triggered from the external trigger port on the digitizer card. This does not seem to be supported by the RFSA vis and I am not sure how to integrate ni-Scope and niRFSA in one application.

Hi Jltetzlaff,
The Clk in and Clk out ports on the 5142 can be used to input and
export a reference clock. You can import this as your sample clock
source over the Clk in by using a simple property node. This is
assuming your using LabVIEW. My main concern is regarding your clock.
If you take a look at page 20 of the reference manual here:
http://www.ni.com/pdf/manuals/374300c.pdf, you can see the PFI lines
follow a very specific digital logic specification (TTL). It looks like your
signal won't be recognized properly by these lines. The lines require
a voltage above 2.0V to register high. There is no minimum frequency
on these PFI lines. The problem is the logic levels. My
recommendation would be to export a start trigger with your AWG to
begin the RFSA session. If I'm misunderstanding the setup, could you
please give more details on devices (model numbers), development
enviroment (LabVIEW etc.), and what connections you require. From what
I understand, you want to sync the RFSA devices with the AWG and DUT.
Perhaps the session from the AWG that is generating the clock can also
export an event to start the AWG to start the RFSA device through PFI 0
or PFI 1. This can be done using the niFGEN Export Signals.vi. The
exported signals by this vi will follow the correct logic accepted by
the 5142 digitizer in the RFSA setup.
I hope this helps,
Paul C.

NI SCOPE troubles (PXIe- 5622)

I've been having this problem since sometime now. I have a PXIe-5663 Vector Signal Analyzer, which has a PXIe - 5622 IF Digitizer module.
Someone recently installed some update on the NI SCOPE driver and now it's nowhere to be found. I cannot find the NI SCOPE front panel. What's worse, I am unable to reinstall the NI SCOPE software through Windows 7 control panel, as it doesn't show up there. I tried uninstalling the whoe RFSA + RFSG software and reinstall it with the device driver DVDs. The system does not allow me to install SCOPE, saying that a higher version is already installed. I really need this to work ASAP, so if someone has a suggestion for me to try out, please reply soon.
Thanks,
Tanuj

Well, for now I found a workaround. Apparently I had Scope 3.5 on the system. Someone upgraded it to 3.6 and then the issues I mentioned started occuring. I tried installing 3.7 and I could upgrade everything. I now can access the Scope front panel.
Although I don't know if I had the latest version, how I would have gone about solving this issue.

LeCroy Scope

I'm using LeCroy WaveRunner 6100A scope and I have a problem with
sequency memory, so maybe you could help me.
It's easy to set the sequence mode on and acquire the waveforms into
the memory. Then I use math function called segment to be able to see
and process segments separately.
I would like to use LabView to do calculations to these waveforms. So
to do that I really need to import those datas from scope program to
LabView. And I don't know how to access those segments in scopes
memory. There might be just a simple command to do it but I just don't
know what it is.
I would really appreciate your help. And if you need more information
to be able to help, don't hesitate to ask.

Please see the post here.
Thanks!
-Matt S.
LabVIEW Integration Engineer with experience in LabVIEW Real-Time, LabVIEW FPGA, DAQ, Machine Vision, as well as C/C++. CLAD, working on CLD and CLA.

RFSA 5660 Programming

I am transmitting a BURST of 200 Packets which contains
DSSS Modulated Data using NI-RFSG 5670.
While receiving this transmitted signal using RFSA-5660.
I am using the normal RFSA Programming flow to control my acquisition. Using Reference nodes, I set my other NI-Scope parameters Ref.Position, Trigger Level, Acquisiton time as required.
Other settings for NI-SCOPE and RFSA being set at default levels, With each acquisition of the BURST,I have a problem in acquiring more than a single packet.
While the keeps generating packets.. Everytime I run my RFSA Vi.. I can acquire a maximum of only one packet.
What setting of RFSA should I change to acquire multiple packets.. let us say 10-20 packets at a time ???
Thanks for your help...

Hi RF_Buzzer,
Would you please attach a "simplified" version of your code that exhibits this behavior? I will try to reproduce this behavior.
Have a great day!
Brooks W.
National Instruments

Weird problem flashing the FPGA

Hi,
I am trying to use Chipscope (Logic Analyzer) for the first time,
I saw the target in the Open Hardware interface right away, I can flash the bitstream and the DONE led turns on as you would expect.
Note I am using a simple design that actually works, I am just putting Chipscope to the test.
I turned the board to JTAG boot mode, as I flash the FPGA the ILA is stuck waiting for a trigger: I am monitoring a TLAST bit which I know behaves well. I am also monitoring this bit on a real scope at the same time: nothing happens!
I switched back to Linux (SD card boot mode), transfer this bitstream and flash the FPGA:
cat bitstream.bit > /dev/xdevcfg
and the signal triggers on the scope!
Is it possible that the JTAG interface does not flash the FPGA properly?
I am working on the ZC706 board,
I did not install any particular cable drivers as it worked right away (Debian).
I unplugged any non-JTAG compliant device plugged in the FMC connectors.
The ILA is clocked by an external clock (ideally at 300MHz but I slow it down).
I am using the Synthesis 'Mark Debug' interface which modifies my top .xdc file.
I noticed the default frequency for the ILA is 300MHz, I've had trouble with this value I could not flash the FPGA, downgrading to 50MHz solved the problem.
Any inputs would be appreciated..

Hi Austin, thanks for your help.
So, I presume you mean you are programming the device?
Yes I am programming the device.
Which bitsstream file did you use through JTAG?
project/projects.run/impl_1/design_1_wrapper.bit
Was the exact same on ewritten to the SD card?
Yes: I did cat design_1_wrapper.bit < /dev/xdevcfg as usual.
Is there a debug core also specified when using JTAG?
This bitstream does contain a debug core (ILA + DBG)
<edit>
Do I need to program the CPU to get an FPGA based design probed? I am not using a Zynq clock.
I am obviously lacking a bootloader in the JTAG configuration

How do I file Bug Report? Labview FPGA

I'm not sure if this is a software bug or what, but I'm trying to run the Analog Input example project for Labview FPGA , in "Find Examples >> Hardware Input and Output >> R Series >> Basic IO >> Analog Input - R Series".
The thing is, it works.. mostly.. I manage to send in a sine wave, and see it. However, every now and then, when I set teh Waveform Graph X-axis to autoscale, and change the Update Mode, every time I put it into mode Scope Chart, it freezes my computer, and I have to physically power off my computer and power it back up (which i'm not happy about). I'm using the default settings for the example, my card is in RSE mode, input signal at 25 Hz, 4V p-p
I doubt anyone can guess why this is happening, but is there any way to file a bug report?
Thanks,
Hardware: Quad-core Xeon 2.33 Ghz, 8 GB RAM, PXI-7583R FPGA, PXI-1036 Chassis
Software: Labview 8.6.1, LAbview FPGA 8.6., Vista 64-bit
NI Hardware: PXI-7853R, PCI-5122, PCI-6733, PXI-1036, PCI-MIO-16E-4, PCI-6110
Computer Hardware: Xeon Quad Core - 2.33 Ghz, 8 GB RAM
Software: Labview 2009, Labview FPGA 2009, Vista 64-bit, MAX 4.6, DAQmx 9.0, NI-SCOPE 3.5

1... Adding an unrelated question to a 3-month old post is not the best way to get your questions answered.
Start your own thread next time.
2... The example works fine for me. The EQUALS function works just fine for strings. Be aware of some things, though:
Case matters. If you want to ignore case, then uppercase both strings (or lowercase them) before comparing.
Length matters "X" is not the same as "X ". "123" is not the same as "1234".
Steve Bird
Culverson Software - Elegant software that is a pleasure to use.
Culverson.com
Blog for (mostly LabVIEW) programmers: Tips And Tricks

RFSA, SCOPE & FPGA

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