Weird problem flashing the FPGA

Question

Hi,
I am trying to use Chipscope (Logic Analyzer) for the first time,
I saw the target in the Open Hardware interface right away, I can flash the bitstream and the DONE led turns on as you would expect.
Note I am using a simple design that actually works, I am just putting Chipscope to the test.
I turned the board to JTAG boot mode, as I flash the FPGA the ILA is stuck waiting for a trigger: I am monitoring a TLAST bit which I know behaves well. I am also monitoring this bit on a real scope at the same time: nothing happens!
I switched back to Linux (SD card boot mode), transfer this bitstream and flash the FPGA:
cat bitstream.bit > /dev/xdevcfg
and the signal triggers on the scope!
Is it possible that the JTAG interface does not flash the FPGA properly?
I am working on the ZC706 board,
I did not install any particular cable drivers as it worked right away (Debian).
I unplugged any non-JTAG compliant device plugged in the FMC connectors.
The ILA is clocked by an external clock (ideally at 300MHz but I slow it down).
I am using the Synthesis 'Mark Debug' interface which modifies my top .xdc file.
I noticed the default frequency for the ILA is 300MHz, I've had trouble with this value I could not flash the FPGA, downgrading to 50MHz solved the problem.
Any inputs would be appreciated..

Answer 1

 
Hi Austin, thanks for your help.
So, I presume you mean you are programming the device?
Yes I am programming the device.
Which bitsstream file did you use through JTAG?
project/projects.run/impl_1/design_1_wrapper.bit
Was the exact same on ewritten to the SD card? 
Yes: I did cat design_1_wrapper.bit < /dev/xdevcfg as usual.
Is there a debug core also specified when using JTAG?
This bitstream does contain a debug core (ILA + DBG)
<edit>
Do I need to program the CPU to get an FPGA based design probed? I am not using a Zynq clock.
I am obviously lacking a bootloader in the JTAG configuration