Sending text / image to bluetooth device from PC to mobile

im developing a java application whereby it will send text file and also an image files from a PC to mobile using bluetooth technology.
can someone show me how i can send the file in parallel to more than one mobile per time without having to wait the receiver to accept or reject the message which was sent to them???
pls help :( thx in advance :)

Hi Tapan,
well, if I would have to do that..... I would at least need Sybase to keep development low. at the end you do not really need Sybase for this... but without SUP development effort is really high.
Okay, in short:
each device has its wn dedicated listener concept for push messages. This is platform dependend and you need to develop a native solution for this. It is possible, but it takes some time.
If you want to be native, with Sybase you get this more or less for free. Issue here: Sybase does only support push notifications out of the box in the most complex scenario: therefore you need SAP backend, Netweaver Mobile Middleware, SUP and connect NW Mobile and SUP by ESDMA file. This gives you push from backend to device for free on nearly all plattforms out of the box.
So at the end the first question qould be: how much do you want to develop?
Or is it wnough for you to have SUP workflow? Benefit on Workflow: development effort is low, works out of the box, is multi plattform - but like every sunshine there is some shadow - performance of this approach is not really nice. Anyway, it could solve your issue: you receive an eMail in your device, this opens the workflow app and you can accept or decline for example a travel request.
Would that elp?
Regards,
Oliver

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity random is
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Port ( clk :in STD_LOGIC;
output : out STD_LOGIC);
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signal counter: integer:=0;
begin
process (clk)
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output <= '1';
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output <= '0';
elsif counter=105 then
output <= '0';
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end process;
end Behavioral;
----------------------------------------------------------------------UART RX
-- File Downloaded from http://www.nandland.com
-- This file contains the UART Receiver. This receiver is able to
-- receive 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When receive is complete o_rx_dv will be
-- driven high for one clock cycle.
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
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use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity receive is
generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
port (
i_clk : in std_logic;
i_rx_serial : in std_logic;
o_rx_dv : out std_logic;
o_rx_byte : out std_logic_vector(7 downto 0)
end receive;
architecture rtl of receive is
type t_SM_MAIN is (s_IDLE, s_RX_START_BIT, s_RX_DATA_BITS,
s_RX_STOP_BIT, s_CLEANUP);
signal r_SM_MAIN : t_SM_MAIN := s_IDLE;
signal r_RX_DATA_R : std_logic := '0';
signal r_RX_DATA &colon; std_logic := '0';
signal r_CLK_COUNT : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_BIT_INDEX : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_RX_BYTE : std_logic_vector(7 downto 0):= (others => '0');
signal r_RX_DV : std_logic := '0';
begin
-- Purpose: Double-register the incoming data.
-- This allows it to be used in the UART RX Clock Domain.
-- (It removes problems caused by metastabiliy)
p_SAMPLE : process (i_clk)
begin
if rising_edge(i_clk) then
r_RX_DATA_R <= i_rx_serial;
r_RX_DATA <= r_RX_DATA_R;
end if;
end process p_SAMPLE;
-- Purpose: Control RX state machine
p_UART_RX : process (i_clk)
begin
if rising_edge(i_clk) then
case r_SM_MAIN is
when s_IDLE =>
r_RX_DV <= '0';
r_CLK_COUNT <= 0;
r_BIT_INDEX <= 0;
if r_RX_DATA = '0' then -- Start bit detected
r_SM_MAIN <= s_RX_START_BIT;
else
r_SM_MAIN <= s_IDLE;
end if;
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when s_RX_START_BIT =>
if r_CLK_COUNT = (g_CLKS_PER_BIT-1)/2 then
if r_RX_DATA = '0' then
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r_SM_MAIN <= s_RX_DATA_BITS;
else
r_SM_MAIN <= s_IDLE;
end if;
else
r_CLK_COUNT <= r_CLK_COUNT + 1;
r_SM_MAIN <= s_RX_START_BIT;
end if;
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when s_RX_DATA_BITS =>
if r_CLK_COUNT < g_CLKS_PER_BIT-1 then
r_CLK_COUNT <= r_CLK_COUNT + 1;
r_SM_MAIN <= s_RX_DATA_BITS;
else
r_CLK_COUNT <= 0;
r_RX_BYTE(r_BIT_INDEX) <= r_RX_DATA;
-- Check if we have sent out all bits
if r_BIT_INDEX < 7 then
r_BIT_INDEX <= r_BIT_INDEX + 1;
r_SM_MAIN <= s_RX_DATA_BITS;
else
r_BIT_INDEX <= 0;
r_SM_MAIN <= s_RX_STOP_BIT;
end if;
end if;
-- Receive Stop bit. Stop bit = 1
when s_RX_STOP_BIT =>
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_CLK_COUNT < g_CLKS_PER_BIT-1 then
r_CLK_COUNT <= r_CLK_COUNT + 1;
r_SM_MAIN <= s_RX_STOP_BIT;
else
r_RX_DV <= '1';
r_CLK_COUNT <= 0;
r_SM_MAIN <= s_CLEANUP;
end if;
-- Stay here 1 clock
when s_CLEANUP =>
r_SM_MAIN <= s_IDLE;
r_RX_DV <= '0';
when others =>
r_SM_MAIN <= s_IDLE;
end case;
end if;
end process p_UART_RX;
o_rx_dv <= r_RX_DV;
o_rx_byte <= r_RX_BYTE;
end rtl;
TOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
port(cl_k: in std_logic
end top;
architecture Behavioral of top is
--component random
component random is
generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
Port ( clk :in STD_LOGIC;
output : out STD_LOGIC
end component;
--component uart rx
component receive is
generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
port (
i_clk : in std_logic;
i_rx_serial : in std_logic;
o_rx_dv : out std_logic;
o_rx_byte : out std_logic_vector(7 downto 0)
end component;
--signal
signal mlebu:std_logic;
signal enabl:std_logic;
signal metu :std_logic_vector (7 downto 0);
begin
a:random port map( output=>mlebu,
clk=>cl_k
b:receive port map( i_clk=>cl_k,
i_rx_serial=>mlebu,
o_rx_dv=>enabl,
o_rx_byte=>metu
end Behavioral;
regards
halim

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