Simple Project Simulation Example

Question

Lets Consider a simple full adder project:
`timescale 1ns / 1ps
module add(var1,var2,add,clk,cin,cout);
input [3:0] var1;
input [3:0] var2;
output reg [3:0] add;
input clk;
input cin;
output reg cout;
always @ (posedge clk) begin
{cout,add}=var1+var2+cin;
end
endmodule
This this the adder module
`timescale 1ns / 1ps
module top();
reg [3:0] var1;
reg [3:0] var2;
wire [3:0] add;
reg cin;
wire cout;
reg clk=0;
add A1(.cin(cin),.cout(cout),.add(add),.var1(var1),.var2(var2),.clk(clk));
initial begin
var1=3;
var2=2;
cin=1;
end
initial #2 $finish;
initial begin
forever
#1 clk=~clk;
end
endmodule
This code is only used for simulation purpose.
Can anybody explain what mistake i am doing?
I have attached the snapshots for Behavioural simulation,Post synthesis functional Simulation and Post synthesis Timing Simulation.

Answer 1

HI,
When you create a test bench, remember that the GSR pulse occurs automatically in the post-synthesis and post-implementation simulation. This holds all registers in reset for the first 100 ns of the simulation.
As mentioned by muzaffer you are not waiting long enough to get out of the GSR condition.
Change the initial statemnet as below and you will be able to see the expected results.
initial #102 $finish;
For more details on GSR please refer to below user guide Global set and Reset section.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug900-vivado-logic-simulation.pdf
The following bullets are recommendations for creating an effective test bench.
• Always specify the `timescale in Verilog test bench files.
• Initialize all inputs to the design within the test bench at simulation time zero to properly begin simulation with known values.
• Apply stimulus data after 100ns to account for the default Global Set/Reset (GSR) pulse used in UNISIM and SIMPRIMS-based simulation.
• Begin the clock source before the Global Set/Reset (GSR) is released