Strange number from pxi 6608

We are using the PXI 6608 card with a six channel system
involving counters. When we run the program we get a very large count,
somewhere around 40million, and it the same number every time. The problem is
that there is no way that can be a real count. We do get other counts that seem
to be actual data but every couple of cycles this large number occurs .Our
counters our connected to a kill switch, programmed in LabVIEW that will cut
the power to the counters if they reach the maximum number of counts we have
set. We know the kill switch is working because we have measured counts that
cut the power. However, when this large number comes up nothing happens and the
counters remain on and our limit is set far below 40million. Has anyone seen
this or other instances like it?
Thanks

Hi,
At the moment I am not sure why your problem is occuring but am happy to look into the matter for you when I have a bit more information.
What version of LabVIEW are you using?
How is the PXI system set up? For example are you connecting remotely from a host PC using LabVIEW realtime or are you booting the system into windows?
Would you be able to provide an example VI and any project files that demonstrate the problem?
Tom Clark
Message Edited by ThomasC on 08-06-2008 11:01 AM
Applications Engineer
National Instruments UK & Ireland

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Performance verification PXI 6608

Hi,
I have a question about the performance verification of the PXI 6608.
This is what I was able to perceive from the manual.
We have two modules:
CTR0: referenced to an external clock that has a minimum uncertainty of 0.75 ppb and generates a 400 s pulse to CRT1.
CTR1: is referenced to the internal 10 MHz OCXO and counts the number of cycles in that 400 s window: 400 * 10 MHz=4*10^9 . Any result different from this means an error.
Now to my understanding the performance verification is comparing the 10 MHz OCXO with the external clock. So by looking at the manual we have a uncertainty of 75ppb when the 10 MHz OCXO is on the slot 2: 0.75ppb * 10 MHz = +/- 0.75 Hz. BUT the performance verification assumes a tolerance of 0.1 Hz (10,000,000.1 < Hz < 9,999,999.9 Hz)
The calibration execute has the same approach as the performance verification,
Why does the PXI 6608 have a tolerance different from the manual?
Are we not testing the 10 MHz OCXO?

Hi,
Thanks for your suggestion but my Qauestion is lillte bit different.
1) We have Equipment master in PM module.
2) Calibration scenario already mapped in PM with maintainance oreder with "14" inpsection type.
3) This is related to performance verification which is different from Calibration scenario.
4) i dont understand that what we have to do in QA05?
5) I want another inspection lot for "Performance verification" except "14".
6) We have defined frequency with test paramater. e.g. HPLC have PV frequency 3 month, 6 month & 12 month with different test parameter.
7) now i want that at each time point, i required auto generation of inpsetcion lot with defiened inspection plan in QA32. After testing will be completed, we will give UD and declare as this Equipment is Qaulified.
It is different from Calibration scenario.
Calibration actvity done by PM member but perfomance activity monitor by QA (QM) person.
Pls help me to design this scenario.
Thanks & Regards,
Ms. Kruti Shah

PXI-6608 specifications

Hi,
I have a question about the performance verification of the PXI 6608.
This is what I was able to perceive from the manual.
We have two modules:
CTR0: referenced to an external clock that has a minimum uncertainty of 0.75 ppb and generates a 400 s pulse to CRT1.
CTR1: is referenced to the internal 10 MHz OCXO and counts the number of cycles in that 400 s window: 400 * 10 MHz=4*10^9 . Any result different from this means an error.
Now to my understanding the performance verification is comparing the 10 MHz OCXO with the external clock. So by looking at the manual we have a uncertainty of 75ppb when the 10 MHz OCXO is on the slot 2: 0.75ppb * 10 MHz = +/- 0.75 Hz. BUT the performance verification assumes a tolerance of 0.1 Hz (10,000,000.1 < Hz < 9,999,999.9 Hz)
The calibration execute has the same approach as the performance verification,
Why does the PXI 6608 have a tolerance different from the manual?
Are we not testing the 10 MHz OCXO?

Hello,
In order to set the counter source to the timebase, you can use the the get/set/reset CI_CtrTimebaseSrc in order to set this in CVI. Please consult the DAQmx C reference Help for more information. Here are the functions if you can't find it in the help.
int32 __CFUNC DAQmxGetCICtrTimebaseSrc(TaskHandle taskHandle,
const char channel[], char *data, uInt32 bufferSize);
int32 __CFUNC DAQmxSetCICtrTimebaseSrc(TaskHandle taskHandle,
const char channel[], const char *data);
int32 __CFUNC DAQmxResetCICtrTimebaseSrc(TaskHandle taskHandle,
const char channel[]);
As for performing a loopback test to test its accuracy, this isn't the best way to do this because the source is creating a signal with relatively the same accuracy as you are reading in back on the same device. Knowing that this signal is accurate down to .7ppm, we need to apply a source for the counter that is much more accurate than this. First way to do this is to change the timebase source to the 10MHz clock like I mentioned above. The other way is to place the PXI-6608 in slot 2 so that it overwrites the 10MHz clock on the backplane. This 10MHz clock is used with PLLing the 80MHz clock that is normally used in counter tasks. Which slot do you have the PXI-6608 in? Could it be placed in this slot?
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National Instruments
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Auto switch to BNC ref-in to replace backplane 10MHz if detected clock signal there with PXI-6608 on Slot2

Hi,
I m using chassis PXI-1045. The priority of backplane frequency is Slot 2 => Ref-In => Origin Backplane 10MHz.
But I wanted the backplane frequency to be in the priority order of Ref-In => Slot 2 => Origin Backplane 10MHz.
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engwei

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I've checked with R&D, and the priority of the clock selection is embedded in the firmware on the backplane. So unfortunately it is not possible to change the priority via software.
As far as the DAQmx functions are concerned, I did a check but was also not able to find any function that can disable the NI 6608 clock from being used to override the PXI backplane clock.
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Though this was long time ago already I need confirmation on the same kind of calculations.
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Strange number from pxi 6608

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