Too many backlog in DMA FIFO

Question

Hi I am using DMA FIFO for data aquisition. When I only have the data showing on the front panel, the data value is reasonable and the backlog value is around 3. But when I have the write to measurement file block in the block diagram, the back log value will rise to several thousands. How should I make the change to the program to reduce the backlog.
Attachments:
fpgaAcquire.vi ‏108 KB
fpgaAcquire(host).vi ‏187 KB
DMA_FIFO.lvproj ‏193 KB

Answer 1

Buddy Haun wrote:
I looked at your code and you don't have the code you are using to write to disk on this block diagram. I would make sure that your loop time on the fpgaAcquire.vi is set to microseconds instead of ticks which it is currently set to. I would try the TDM Streaming vi's with the Open File and Close file outside the loop so that you are not opening and closing the file inside the loop. There are examples of TDM Streaming in example finder. Lastly if the TDM Streaming cannot be used due to file format restrictions or if it is still not fast enough you may need to create a second loop and use queue vi's to transfer the data. This will allow you to read multiple points from the queue using the flush queue function writing multiple points to the file at once. You will still probably need to open and close the file outside of the second loop. Look at some the Write Datalog File Example.vi to see how to do this.
I did some experiment on the FPGA period. When I set it to be below 400 usec, the data looks almost the same. But when I set it to be above 500 usec. The period of the signal displayed on the screen seems to be multiplied by some constant, and the constant is not proportional to the FPGA period. I will agree with you on using TDMS streaming outside the loop and I will try it.