Ultrascale gen3 core: Bus Master Enable bit cannot be set

Hi, I am running DMA simulation on Ultrascale gen3 core and I find that the Bus Master Enable bit of RP end cannot be set.
In TSK_SYSTEM_INITIALIZATION, the system configures the command register using:
board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h01, 32'h00000007, 4'h1);
This changes the cfg_function_status[15:0] from 16'h0088 to 16'h008b, which means that it only changes bit 0 and bit 1, but does not change the bus master enable bit.
I tried to use TSK_WRITE_CFG_DW to write to command register againt, but it seems that only bit 0 and bit 1 can be modified. How can I solve this bug? Many thanks!
Pei Luo

Hi, Vanitha,
Thanks for your response!
I am using Xilinx RC model. I also find that TSK_WRITE_CFG_DW takes negative byte enable, but I think this is a bug here. In gen2 PCIE RC model, it used to be negative enable, but in gen3 it should be positive enable. I tried to use negative enable in the code and it does not work here.
Thanks!
Pei

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