Usage of generated clocks

Question

I am very new to FPGAs , sorry, if there is a place that explains this from the beginning (book or user guide).  I'll appreciate any pointers. I am trying to create a simple flip-flop, and I am using a 100MHZ clock:
My constraint file looks like this for that part:
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }];
create_clock -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
I want to use a clock that is divided by 2 (50MHZ) , so I looked around and there is a way to generate a clock derived from the primary one above, so I added the third line you see below to the above two lines:
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }];
create_clock -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
create_generated_clock -name clkdiv2 -source [get_ports CLK100MHZ] -divide_by 2 [get_pins REGA/Q];
How can I now use this clkdiv2 clock in my Verilog Design?. I am assuming I have to create an instance of REGA?
Something like this?:
module D_ff_behavior
        input D,
        input CLK100MHZ,
        output reg Q
    input wire clk_div_2; ???
    REGA REGA_FF(.D(??), .Q(clk_div_2),.C(CLK100MHZ))
    //assign LED1=CLK100MHZ;
    always @ (posedge clk_div_2)
        Q <= D;
endmodule

Answer 1

I was able to run a derived clock using the MMCM. I took the primary 100MHZ and obatined a 50MHZ (also re-did it for 5MHZ) and it worked. I used the Clock Wizard, which generates an MMCM with my desired characteristics, obviously I have to learn much more on the different choices, but made it to work, I downlod it (no warnings and no errors) and measured it with the oscilloscope and the clock signal measured what I set it to.
If there is something suspicious or a bad practice in this code, please let me know,
Below is the Constraint XDC File followed by the Verilog code, for the 5MHZ case (divided by 20):
# Swithch used for D
## Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }];
create_clock -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
create_generated_clock -source [get_ports CLK100MHZ] -divide_by 20 [get_pins MMCM0_instance/clk_out1];
#Switche to set D of the simple D-FF
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports { D }];
#LED0 to see the output of the simple D FF
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports { Q }];
# LED1 used to see the output of the divided clock
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports { LED1 }];
Verilog Code:
`timescale 1ps / 1ps
// Module Name: D Flip Flop    
module D_ff_behavior
        input D,
        input CLK100MHZ,
        output reg Q,
        output LED1
    wire clk_div_2;
    assign LED1=clk_div_2;
    MMCM0 MMCM0_instance(.clk_in1(CLK100MHZ),.clk_out1(clk_div_2));
    always @ (posedge clk_div_2)
        Q <= D;
endmodule
I guss I still don;nt understand how are the commands in the XDC used. I mean didn't I configured the MMCM with clock Wizard?, why do I have to put the create_generated_clock _ command in the XDC file, I know there is a reason, I am just missing something, so far seems redundant info...