FPGA Base Clocks PCI-5640R

Hi,
     I am using NI PCI-5640R. Following FPGA Base Clocks are available to me:
(1)   Configuration_Clk
(2)   RTSI_Ref_Clk
(3)   DAC_0_IQ_Clk
(4)   DAC_1_IQ_Clk
(5)   ADC_0_Port_A_Clk
(6)   ADC_1_Port_A_Clk
Can anyone help me with brief descriptions of each clock? When these clocks are to be used?
Kindly send me some URL links where I can find details about the usage of these clocks?
Thanks and Regards,
Rashid
Solved!
Go to Solution.

Hello Rashid,
(1) Configuration_Clk - This is 20MHz onboard clock, which runs independently of the other clocks. The role of the 20MHz configuration_clk is to provide a fixed frequecny configuration clock that is use by STC2 ASCI for PCI-DMA operations. Also this clock is not synchronized to the 200MHz VCXO or to the external clock
(2) RTSI_Ref_Clk - This is a device reference clock derived from 200MHz internal VCXO, by setting the dividing factor ranging from 1,2,4,8 and 16.
The I/Q clocks are the signals that indicate the rate of the baseband data. These clocks indicate the rate of the data before the digital upconversion in DAC and the rate of the data after the digital downconversion for ADC. They are described as below.
(3) DAC_0_IQ_Clk and (4) DAC_1_IQ_Clk -
 DAC__IQ_Clk = 2 × REFCLKDAC_ × Clock multiplierDAC_ / InterpolationDAC_
where
REFCLKDAC_ is the specified device reference clock / N2 or 3 CDC. Specify the divisor using the ni5640R CDC Program VI.
Clock multiplierDAC_(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R DAC Program VI.
InterpolationDAC_ is the hardware interpolation rate determined by the DAC fixed 4× interpolator times a programmable 2× to 63× CIC interpolating filter. The programmable CIC interpolator can be configured using the ni5640R DAC Profile VI.
(5) ADC_0_Port_A_Clk and (6) ADC_1_Port_A_Clk -
 ADC__Port_A_Clk = ENCADC_ × Clock multiplierADC_ / (Predivide FactorADC_ × DecimationADC_)
where
ENCADC_ is the device reference clock / N0 or 1 CDC. Specify the divisor using the ni5640R Configure Timebase VI.
Clock multiplierADC_(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R Input Port VI.
Predivide FactorADC_ (N) is equal to 1, 2, 4, or 8. Configure the predivide factor using the ni5640R Input Port VI.
DecimationADC_ is the decimation factor for a particular channel in the ADC. Decimation is performed in various filters throughout the processing channel. Each channel includes one CIC filter (decimates by 1 to 32), two FIR-HB filters (each decimates by 2), one DRC filter (decimates by 1 to 16) and one CRCF filter (decimates by 1 to 16). Configure all these filters using the ni5640R ADC Configure DDC VI.
The figure below shows how all the above clocks are derived
Thanks
NI-khil

Similar Messages

Clock of PCI 5640R

Hi!
 I got a little bit confused by the clock of PCI 5640R.
 What does "nominal frequency" which appears when I add a clock in in the Project Explorer mean?
 How does it come into play with the following equation?
 DAC__IQ_Clk = 2 × REFCLKDAC_ × Clock multiplierDAC_ / InterpolationDAC_
 Thanks!
Dayu

Hi Dayu
The "nominal frequency" field in the Project Explorer is basically a value that the Xilinx tools use to determine if the FPGA code will run on the FPGA. In the process of compiling the code, it will determine the maximum speeds that portions of the circuit will run at. Say you specific 75.0 MHz. If Xilinx thinks the circuit can run at 100 MHz, there are no problems, but if Xilinx thinks that the circuit’s maximum speed is ~70 MHz, it will fail.
You should only have to change this if your FPGA code can’t run at the default number and you want to clock the circuit at a much slower rate. Then put in a value higher than the rate you are going to clock it, and lower than what the Xilinx tools say is the maximum rate for your code.
This value does not really factor into the DAC__IQ_Clk equation, which is configured with the Clock and DAC configuration VIs.
Jerry

Multiple issues with PCI-5640R FPGA: DAC and Strange Execution at Host

We are working on a communications systems project using the PCI-5640R
IF-RIO transceiver and the FPGA module. At the FPGA, a sequence of bits are
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to build this project. There are, however, several issues/questions we
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1. The host only runs every other time. At the host (BPSK_TX(HOST).VI, the execution gets
halted for an infinite period of time at one of the FIFOs until 'stop' is
hit. But then at the subsequent execution, the host completes execution
of the program. In other words, the host is only receiving data from the
FPGA every second time it is run. Why is this happening? Are we missing
something at the host or FPGA VI?
2. How exactly do we send our own digitized signal through
the DAC? As seen in one of the FPGA VIs, we have tried modfiying the
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the FPGA reads from the FIFO. In our case, we are modulating the signal
in a separate section, writing it to a target-scoped FIFO and then reading from
that FIFO and processing the data as in the example. This modified FPGA
vi is "BPSK_TX(FPGA).VI)
Unfotunately, we are not observing anything at an oscilloscope
connected to the transceiver. Even when we try to pass in a
"custom" signal at the HOST we have no luck observing anything
coherent. As seen in the bare_sine_wave_test (FPGA).vi, we have
attempted a relatively simple way of sending a signal through the DAC, yet
still no luck. I am guessing that this is related to issue #1.
On a related note, when
receiving the signal and running it through the ADC, what steps are
necessary? Can one assume that it is
similar to the FPGA.VI in the analog input and output example?
3. How do for loops and while loops synchronize with timed loops
and frames in the FPGA? In the FPGA we are using a for loop to
modulate the signal because the sine wave generator cannot be contained within
a timed loop on the FPGA. This will be important to us because at the
receiver we will need to know the symbol rate in order to recover the signal.
I would sincerely appreciate any feedback or help that can be provided
on this,
Attachments:
BPSK_TX(FPGA).vi ‏152 KB
BPSK_TX(HOST).vi ‏257 KB
bare_sine_wave_test (HOST).vi ‏135 KB

It may be that the FPGA Refernce has not been binded. The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control. This is an option on the popup menu when clicking on the Open FPGA VI Reference VI. In some cases, it may already be selected in the popup menu. In this case, unselect the Bind to Typedef option. For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option. In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI. In some cases, I have to Save All, close the host VI and all subVIs. Then reopen the host VI. This has always working in all cases for me.
Jerry

Using NI PCI-5640R as Real-Time Spectrum Analyzer

Hi,
The code for NI PXIe-5641R Real-Time Spectrum Analyzer demo is posted HERE for LV 2009. I want to use the same code for NI PCI-5640R instead of NI PXIe-5641R. Since I am using a 5640R, I have changed the device in the project.
Can any one guide me what else changes I have to make in this Demo code so that I can use the same code for NI PCI-5640R
instead of NI PXIe-5641R?
Thanks and Regards,
Rashid
Solved!
Go to Solution.

Hi Eug,
It sounds to me like you need to go back and re-install support for LabVIEW 2009 and 2010 through the NI-RFSA driver. You can do this through Add/Remove Programs. Select National Instruments "Change/Remove" and when the pop up window comes up select NI-RFSA and select "Modify." This will re-load the installer for NI-RFSA and through there you can add/remove support for versions of LabVIEW. Make sure that LV 2009 and 2010(if you're using it) are selected.
As for your application, if I understand you correctly your setup goes something like PXI-5600»PXIe-5641R»PXI-5610 (»PXI-5690?). If you're just trying to acquire a signal on the 5641R and amplify it digitally before replaying it on the AO port, then you could try to use the example code "ni5640R Analog Input and Output" that is found here:
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\ni5640R\FPGA\PXIe-5641R\ni5640R Analog Input and Output\
as a base to follow, but you'll need to modify the code so that you're not providing the AO data from the host, instead you'll re-route the AI data on the FPGA through some amplification block and then feed that to the AO port. If you're including the 5600 and 5610 in this process, then that modified example will just need to include some code on the host to setup the 5600 for downconverter only mode and the 5610 for upconverter only mode. There are examples of this that you can find in their respective driver examples:
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\niRFSA\RFSA Downconverter with External Digitizer.vi
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\niRFSG\RFSG External AWG (5610).vi
The addition of these last two pieces of code will make this modified example look a lot like the code that NAyer linked above without the FFT processing.
I hope this helps.
Chris W

Using external time base on PCI-MIO-16XE-50

What is frequency of the internal time base of PCI-MIO-16XE-50? How can I replace it with my external timebase ( a pulse signal from an atom clock)?
Also after replacing the internal timebase with external one, the scan rate and channel convert rate will be based on this external timebase automatically, right? For example, I define 1000 scan/s on AI0-AI8, it will be a scan rate based on the external timebase?

The AI Clock Config.vi can be used to set the scan clock rate. If a person wishes to change the boards internal time base to an external one, the method described in http://digital.ni.com/public.nsf/3efedde4322fef19862567740067f3cc/5601c8268d625a3c86256cf50071199d?OpenDocument is the way to do this.
The PCI-MIO-16XE-50 has a RTSI connector. Please look at the PCI Board JPEG on http://digital.ni.com/public.nsf/websearch/AD2D553F55A07BBF8625650D005F1F00?OpenDocument for the location of this connector. This site also contains a table of the RTSI Connector Pinouts.

PCI-5640R for my thesis

Hi everyone!
First, I apologize for my english, but I'll do my best to be understood
So, I'm starting with my thesis that I have to defend at the end of this year, and my mentor(?) gave me this PCI-5640R card to explore. At this point I must say, that I'm totally rookie with this Even more, I don't even know how to explore it. OK, I installed card in my PC, installed LabVIEW, drivers for the PCI card etc. It gets complicated or frustrated when I try to run some demos - it has always some errors.I read "Gettting started" thing, but still no success A lot of "VIs" is missing while loading example.
All I have to do is to run some demos for PCI-5640R card that will demonstrate it's functions and capabilities. And my thesis is basically done...well, still have to dome reasearch on SDR, DPS, LabVIEW etc.
Any help, suggestions will be more then appreciated!
Best regards from Slovenia!
Senad

SenadMur wrote:
Hi everyone!
First, I apologize for my english, but I'll do my best to be understood
So, I'm starting with my thesis that I have to defend at the end of this year, and my mentor(?) gave me this PCI-5640R card to explore. At this point I must say, that I'm totally rookie with this Even more, I don't even know how to explore it. OK, I installed card in my PC, installed LabVIEW, drivers for the PCI card etc. It gets complicated or frustrated when I try to run some demos - it has always some errors.I read "Gettting started" thing, but still no success A lot of "VIs" is missing while loading example.
All I have to do is to run some demos for PCI-5640R card that will demonstrate it's functions and capabilities. And my thesis is basically done...well, still have to dome reasearch on SDR, DPS, LabVIEW etc.
Any help, suggestions will be more then appreciated!
Best regards from Slovenia!
Senad
Senad,
I think I could better asses what is going on if you tell me what software you are running.
Please tell me your:
Operating System Version?
Operating System 32 or 64bit?
LabVIEW version?
LabVIEW 32bit or 64bit?
Are you using LabVIEW FPGA?
NI-RIO Version?
NI-5640R Driver Version?
These National Instruments software versions can be found in Measurement and Automation Explorer with the exception of the NI-5640R Driver. The NI-5640R driver version can be found by going to control panel >> add/remove programs >> National Instruments Software.
Also, if you write down a few of the missing file names it might help me figure out what is missing.

Pci-5640R Config.ADC 0 Microport Address write error

I am trying to run the tutorial in the "Getting Started with the NI PCI-5640R IF Transceiver and the LabVIEW FPGA Module" document. I got everything set up, but when I run it, I get an error which says
"Error -61059 occurred at Read/Write Control:Config.ADC 0 Microport Address in Simple Spectrum Analyzer.lvlib:ni5640R ADC address_port_write.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC read_write.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC read_write (multi-byte).vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC write_register.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC 01 - Chip IO Access.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC Global.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC Default.vi->Simple Spectrum Analyzer (HOST).vi"
I can't figure out how to fix it.

It may be that the FPGA Refernce has not been binded. The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control. This is an option on the popup menu when clicking on the Open FPGA VI Reference VI. In some cases, it may already be selected in the popup menu. In this case, unselect the Bind to Typedef option. For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option. In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI. In some cases, I have to Save All, close the host VI and all subVIs. Then reopen the host VI. This has always working in all cases for me.
Jerry

Simulation mode for PCI-5640R

Hi,
I am evaluating whether to buy a PCI-5640R (or PXI-5641R) card for a project. I would like to prototype the code first to see if what I want to do would work. Is it possible to use the 5640R driver in simulation mode, without a physical card installed? M-series daq cards support this, is there similar support for 5640R / 5641R/
thanks in advance
greg

Hi Greg,
You can simulate the use of your IF Transceiver code before you make a decision on whether or not to purchase. There are a couple caveats though. First, you must have the NI-5640R driver installed in order to find that device as a simulated device. The other thing is that you'll need to have the LabVIEW FPGA module already purchased and installed. If neither of these are issues, then you are good to go for prototyping. I recently updated the instructions on how to set your IF-RIO FPGA project for simulation that you can find HERE.The updates that I made to include the IF-RIO may not be live yet, but should be up within the next day. Those instructions should get you rolling. Enjoy!
Chris W

MOVED: What is the Safe OC (base clock) for MSI Eplices plus?

This topic has been moved to Overclockers & Modding Corner.
https://forum-en.msi.com/index.php?topic=130206.0

Hi tancheeru, & welcome to the forum. As this is an OC question, the mods will probably move it to the OC & Modders Section of the forum. Please provide a signature with your systems components. It is difficult to make suggestions without it. In most cases I have experienced, base clock at 166 or 167 will most of the time work on default voltage. However, RAM must be adjusted to compensate for it's increase in speed as base clock is increased. This may involve the Mem. Ratio, Uncore Ratio, timings, & DRAM V.

What is the Safe OC (base clock) for MSI Eplices plus?

Default Base clock for this board is 134. How much can i go still consider as safe OC?

Hi tancheeru, & welcome to the forum. As this is an OC question, the mods will probably move it to the OC & Modders Section of the forum. Please provide a signature with your systems components. It is difficult to make suggestions without it. In most cases I have experienced, base clock at 166 or 167 will most of the time work on default voltage. However, RAM must be adjusted to compensate for it's increase in speed as base clock is increased. This may involve the Mem. Ratio, Uncore Ratio, timings, & DRAM V.

PCI 5640R using Both ADCs

Hi,
I am having a difficulty acquiring data from both ADCs on the PCI-5640R. I started with the My Simple Spectrum Analyzer example in the User Guide tutorial and then added the second channel to it as seen in the figure. I didn't observe any errors, but the second FIFO (FIFO 1) comes back empty. Maybe I need ADC1 acquisition to occur in it's own timed loop with the ADC1_clk driving it? Maybe the problem is in the Host VI where I signal for acquisition and then read from FIFO before FIFO1? I'm hoping someone can provide an example to save me compile time in trying to guess my way through it. There must be a lot of people using both inputs!
Chris
Attachments:
DualADCtarget.JPG ‏52 KB

Sorry. I reposted on the IF-RIO board.
Chris

Should I raise the base clock or the multiplier?

I have Intel Core i7 875k
I can reach 4.2Ghz by either raising the multipliers or by raising the base clock
I do prefer to just raise the multiplier since the rest of my system doesn't runs under any extra stress
However, today I read:
We also prefer to use the Base Clock rather than the CPU multiplier when overclocking CPUs. Increasing the Base Clock increases the amount of bandwidth between the CPU and the rest of the system, yielding greater performance for the same overall CPU frequency.
Is that true?
and if it's true, is there a big or a small difference?
I am not sure how big of a difference it will make to run a CPU at 4.2Ghz by either using multipliers or base clock

I run Prime95 and Adobe Premiere CS5 to test stability
With Adobe Premiere CS5 I can have a good idea of how fast the CPU is
Can you tell me which is the best software to test the CPU speed?
I'd like to see some numbers, then I'll get a better idea of what I'm doing

Eclipse SLI: Can't change Base Clock in Bios

Not sure why, but in the Cell Menu in the Bios (v. 1.6) the Base Clock can't be changed - hitting Enter when it's highlighted does nothing. It's not greyed out, just doesn't change.
I looked in the manual and it shows a setting for D.O.T. Control right above the Base Clock setting. But my Bios doesn't have that listed. :(
Any help?

Quote from: Jack t.N. on 26-July-09, 07:47:38
Have you tried the +/- keys (on your keyboard's numpad) or the page-up/page-down keys by any chance...?
Duh...that worked. Thanks!
Although maybe I'm too stoopid to overclock.

Extreme Memory Profile & Base Clock - Resolved

Hi,
I am an Eclipse SLI with BIOS v1.4. When I enable the Extreme Memory Profile, the Base Clock option is no longer visable but I do then get a Ratio option. The only was I can oveclock the CPU is to up the Ration from 20 to 21 and then use the Overclocking Centre within Vista.
Is it a case of one or the other? With the XMP enabled, all 12GB of my RAM runs at 1600MHz just fine.
My obejective is to get my CPU to run at 3.2GHz and have my memory running at 1600MHz - is this possible?
System specification as below - Thanks.

Hi,
Thank you for your suggestion. In the end I raised the base clock to 161 and changed the memory ratio to 5. This gave me 3.2GHz for the CPU and all 12GB of my memory runs at 1600MHz.
Just for others who might read this, you need to have both the Extreme Memory Profile and the Advanced XMP options enabled, as if you only have XMP enabled the Base Clock option for the CPU is not visible.
One last thing, the Nocutura CPU cooler is amazing. Even under load using Flight Simulator X with the overclocking, my CPU never exceeded 35 deg C, the IOH 63 deg C and the system 26 deg C.

MOVED: Base Clock Error Occured + Shut down every 30 minutes

This topic has been moved to Intel Core-iX boards.
https://forum-en.msi.com/index.php?topic=173484.0

I had my motherboard checked by the technicians nearby and found out that my motherboard is a victim of static. Good thing it is still within warranty so they decided to replace it. I have been running my rig for two weeks now and so far neither regular shutdowns nor Base Clock errors were encountered.
My BIOS is still 1.5 and so far I don't have any issues with it.
But just to answer xmad's question:
Is the Ram installed into the 2nd and last DIMM from the CPU?
   Yes, i had this one checked and rechecked
What are the temps during a stress test?
   i forgot.. but it was below 90C
Does the Behavior still occur with a single stick of ram installed into DIMM 2?
   yea, unfortunately

FPGA Base Clocks PCI-5640R

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