VHDL code integration?
Hi everyone,
We've been developing OFDM and SOQPSK-TG transmitter and receiver hardware in FPGA using the design suite. Previously we were using LabVIEW FPGA.
My question is, how do you import pre-written VHDL code to be compiled in the design suite? I cannot seem to figure out how to do this, which was possible with LabVIEW FPGA software. Which type of FPGA-targeted VI would you start with?
Thanks!
-Brian
Solved!
Go to Solution.
I would definitely recommend trying to repair/reinstall VeriStand since you have the code working flawlessly on another set up (could be a corrupt install).
I not familiar with any cRIO hard drive test off the top of my head, but let me look into that and see if we can come up with anything.
Also, for best practices in VeriStand, the closest thing I can recommend is the Getting Started materials but this is probably not helpful to you. The next thing would be the actual training but I understand that may not be doable as well. Just from your description of your architecture, I do not see anything inherently wrong but I would have to take a look at the project itself to know for sure.
Daniel K | NI Applications Engineer | Certified LabVIEW Developer
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LabView fpga VHDL code and compiler
Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer -
I am getting the following error in Windows 8 (and 8.1) when a c++ module that I developed is loaded. I am not getting the error on Windows 7.
"Code integrity determined that the image hash of a file is not valid. The file could be corrupt due to unauthorized modification or the invalid hash could indicate a potential disk device error."
After lots of searching I came across this TechNet article:http://social.technet.microsoft.com/wiki/contents/articles/255.forced-integrity-signing-of-portable-executable-pe-files.aspx#What_is_Force_Integrity_checking
I verified that I added the "/integritycheck" linker parameter and my signing command is using the "/ph" parameter.
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Thanks for posting in MSDN forum.
I am trying to involve some others to help you on this issue. It would be better if you could tell us more about your C++ module. Is it a COM dll or resource dll something? x86 or x64?
I would suggeset try rebuild this C++ module in windows 8 to check if this issue persist, or something else happens?
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I've to admit, that I don't know Labview by now, therefor I've a
question on a topic I couldn't find a satisfying answer on in the internet.
My intention is to control test board using a digital I/O-card (no
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I could synthesize the VHDL-testbench on a FPGA-Board, but I would
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My question is: Is it possible to implement VHDL-Entities in LabView?
If yes, which LavView Modules do a need? I've read something about a
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Is there a way to do that with Labview?
Thanks,
AndreasIt sounds like your are asking for the ability to use LabVIEW to simulate your VHDL files. You would then use these HDL simulation results as digital test vectors for a DIO board. LabVIEW today does not natively include this capabiliity. I believe you have a few options:
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2 - Use the NI Digital Waveform Editor to import your simulation output as a test vector. You can then verify the waveforms, make any changes, and save it for use with your DIO board. Here is a link: http://sine.ni.com/nips/cds/view/p/lang/en/nid/13050
3 - The HDL node available in LV FPGA allows you to synthesize custom HDL into a LV FPGA target. If you prefer the DIO board as your interface, then this would not work for you.
Based on your notes, I would look into the Digital Waveform Editor's VCD importing feature first (option 2 above).
Which DIO board are you using? And what do you use for VHDL simulation/synthesis for your test board?
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Hello,
I have to import VHDL code in Labview. I would like to know what is the best solution betveen CLIP, IP Node integration or HDL node of the previous version of Labview if it is possible to use it.
Thank you
Solved!
Go to Solution.Hello,
I think those documentations will help you to choose, depending on your requirements:
Difference Between CLIP Node and HDL Node
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I am currently using the free 2 client Perforce software with LabVIEW. It works well for my needs, as we have only 2 developers working on this project. However, we were just got bought out by a larger company that uses Serena PVCS for their version control. We are transitioning to their IT system and I need to transfer everything to a new server anyway, so was considering trying PVCS instead.
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