AXI slave connection of PCIe AXI bridge IP

Question

Hi:  
I'm creating a system with IPI which have Microblaze, DDR3 and PCIe interface.
When connecting the AXI PCIe bridge block, I got some problem.
Currently, I can access DDR3 through PCIe.
The path is Host PC ==> PCIe ==> AXI PCIe bridge ==> AXI interconnect ==> DDR3.
Now, I want to send data from Microblaze to Host PC as well, but don't know how to do it.
Tthe path I think should be : MicroBlaze ==> AXI interconnect ==> AXI PCIe bridge ==> PCIe ==> Host PC.
How should I connect the S_AXI_CTL and S_AXI port on AXI PCIe bridge?
Should S_AXI_CTL be connected? Is it also connected to M_AXI port of AXI interconnect?
Thanks a lot! 
David

Answer 1

This setup looks a bit dangerous because you are mapping PCIe->AXI to address 0x00000000 which will inturn get decoded and go back out to PCIe land.
The M_AXI port from pcie probably only needs access to mig and maybe uart. The microblaze Data port address space looks correct. Any access from microblaze to address 0x00000000 will get decoded by the interconnect and passed to the S_AXI port on the pcie bridge. Then, the pcie bridge translates the axi address 0x00000000 to the PCIe address 0xFF000000.
I'm not a PCIe guru but I believe the software on the host will need to configure its pcie bridge in order to allow access to motherboard resources from the development board. On a linux host, the pcie driver would be responsible to map host memory or motherboard resources to be accessable from the development board.