Clock of PCI 5640R

Hi!
 I got a little bit confused by the clock of PCI 5640R.
 What does "nominal frequency" which appears when I add a clock in in the Project Explorer mean?
 How does it come into play with the following equation?
 DAC__IQ_Clk = 2 × REFCLKDAC_ × Clock multiplierDAC_ / InterpolationDAC_
 Thanks!
Dayu

Hi Dayu
The "nominal frequency" field in the Project Explorer is basically a value that the Xilinx tools use to determine if the FPGA code will run on the FPGA. In the process of compiling the code, it will determine the maximum speeds that portions of the circuit will run at. Say you specific 75.0 MHz. If Xilinx thinks the circuit can run at 100 MHz, there are no problems, but if Xilinx thinks that the circuit’s maximum speed is ~70 MHz, it will fail.
You should only have to change this if your FPGA code can’t run at the default number and you want to clock the circuit at a much slower rate. Then put in a value higher than the rate you are going to clock it, and lower than what the Xilinx tools say is the maximum rate for your code.
This value does not really factor into the DAC__IQ_Clk equation, which is configured with the Clock and DAC configuration VIs.
Jerry

Similar Messages

External Reference Clock on pci-5640R

Hi. I want to clock my IF-RIO 5640R board, with an external reference clock at 2MHz frequency and i would to generate a 200 MHz clock inside the board (as the vcxo).
If I set properly the parameters inside the "configuration timebase" vi, using the pll on the cdc7005, can i achieve this feature?
How can i do?
Thanks....

If you use the fixed-personality driver, and you are feeling a little bit brave, you should be able to use ni5640R Configure Timebase.vi. It can be found (at least on my computer) at:
C:\Program Files\National Instruments\LabVIEW 8.2\instr.lib\ni5640R\Driver\NI-5640R VIs
Leave the defaults as they are, except change as follows:
Ref Divider (M) = 2 (for 2 MHz)
SMB Ext Ref Enable = True
VCXO Control = PLL
CP Enable = True
That should be everything, to the best of my memory. You may have to enable the Invert CP bit.
Hope this helps,
Ed

FPGA Base Clocks PCI-5640R

Hi,
 I am using NI PCI-5640R. Following FPGA Base Clocks are available to me:
(1) Configuration_Clk
(2) RTSI_Ref_Clk
(3) DAC_0_IQ_Clk
(4) DAC_1_IQ_Clk
(5) ADC_0_Port_A_Clk
(6) ADC_1_Port_A_Clk
Can anyone help me with brief descriptions of each clock? When these clocks are to be used?
Kindly send me some URL links where I can find details about the usage of these clocks?
Thanks and Regards,
Rashid
Solved!
Go to Solution.

Hello Rashid,
(1) Configuration_Clk - This is 20MHz onboard clock, which runs independently of the other clocks. The role of the 20MHz configuration_clk is to provide a fixed frequecny configuration clock that is use by STC2 ASCI for PCI-DMA operations. Also this clock is not synchronized to the 200MHz VCXO or to the external clock
(2) RTSI_Ref_Clk - This is a device reference clock derived from 200MHz internal VCXO, by setting the dividing factor ranging from 1,2,4,8 and 16.
The I/Q clocks are the signals that indicate the rate of the baseband data. These clocks indicate the rate of the data before the digital upconversion in DAC and the rate of the data after the digital downconversion for ADC. They are described as below.
(3) DAC_0_IQ_Clk and (4) DAC_1_IQ_Clk -
 DAC__IQ_Clk = 2 × REFCLKDAC_ × Clock multiplierDAC_ / InterpolationDAC_
where
REFCLKDAC_ is the specified device reference clock / N2 or 3 CDC. Specify the divisor using the ni5640R CDC Program VI.
Clock multiplierDAC_(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R DAC Program VI.
InterpolationDAC_ is the hardware interpolation rate determined by the DAC fixed 4× interpolator times a programmable 2× to 63× CIC interpolating filter. The programmable CIC interpolator can be configured using the ni5640R DAC Profile VI.
(5) ADC_0_Port_A_Clk and (6) ADC_1_Port_A_Clk -
 ADC__Port_A_Clk = ENCADC_ × Clock multiplierADC_ / (Predivide FactorADC_ × DecimationADC_)
where
ENCADC_ is the device reference clock / N0 or 1 CDC. Specify the divisor using the ni5640R Configure Timebase VI.
Clock multiplierADC_(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R Input Port VI.
Predivide FactorADC_ (N) is equal to 1, 2, 4, or 8. Configure the predivide factor using the ni5640R Input Port VI.
DecimationADC_ is the decimation factor for a particular channel in the ADC. Decimation is performed in various filters throughout the processing channel. Each channel includes one CIC filter (decimates by 1 to 32), two FIR-HB filters (each decimates by 2), one DRC filter (decimates by 1 to 16) and one CRCF filter (decimates by 1 to 16). Configure all these filters using the ni5640R ADC Configure DDC VI.
The figure below shows how all the above clocks are derived
Thanks
NI-khil

Multiple issues with PCI-5640R FPGA: DAC and Strange Execution at Host

We are working on a communications systems project using the PCI-5640R
IF-RIO transceiver and the FPGA module. At the FPGA, a sequence of bits are
being modulated through multiplication with the sine wave generator. The
next step is to take the modulated sinusoidal signal and send it through the
DAC. Throughout this project, we have been using the Analog Input and Output
example project from Getting Started with the 5640-R IF... as a template
to build this project. There are, however, several issues/questions we
have. Attached are the HOST and FPGA vis that we are working with.
1. The host only runs every other time. At the host (BPSK_TX(HOST).VI, the execution gets
halted for an infinite period of time at one of the FIFOs until 'stop' is
hit. But then at the subsequent execution, the host completes execution
of the program. In other words, the host is only receiving data from the
FPGA every second time it is run. Why is this happening? Are we missing
something at the host or FPGA VI?
2. How exactly do we send our own digitized signal through
the DAC? As seen in one of the FPGA VIs, we have tried modfiying the
output section of the FPGA VI in the Analog Input and Output project in which
the FPGA reads from the FIFO. In our case, we are modulating the signal
in a separate section, writing it to a target-scoped FIFO and then reading from
that FIFO and processing the data as in the example. This modified FPGA
vi is "BPSK_TX(FPGA).VI)
Unfotunately, we are not observing anything at an oscilloscope
connected to the transceiver. Even when we try to pass in a
"custom" signal at the HOST we have no luck observing anything
coherent. As seen in the bare_sine_wave_test (FPGA).vi, we have
attempted a relatively simple way of sending a signal through the DAC, yet
still no luck. I am guessing that this is related to issue #1.
On a related note, when
receiving the signal and running it through the ADC, what steps are
necessary? Can one assume that it is
similar to the FPGA.VI in the analog input and output example?
3. How do for loops and while loops synchronize with timed loops
and frames in the FPGA? In the FPGA we are using a for loop to
modulate the signal because the sine wave generator cannot be contained within
a timed loop on the FPGA. This will be important to us because at the
receiver we will need to know the symbol rate in order to recover the signal.
I would sincerely appreciate any feedback or help that can be provided
on this,
Attachments:
BPSK_TX(FPGA).vi ‏152 KB
BPSK_TX(HOST).vi ‏257 KB
bare_sine_wave_test (HOST).vi ‏135 KB

It may be that the FPGA Refernce has not been binded. The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control. This is an option on the popup menu when clicking on the Open FPGA VI Reference VI. In some cases, it may already be selected in the popup menu. In this case, unselect the Bind to Typedef option. For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option. In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI. In some cases, I have to Save All, close the host VI and all subVIs. Then reopen the host VI. This has always working in all cases for me.
Jerry

PCI 5640R using Both ADCs

Hi,
I am having a difficulty acquiring data from both ADCs on the PCI-5640R. I started with the My Simple Spectrum Analyzer example in the User Guide tutorial and then added the second channel to it as seen in the figure. I didn't observe any errors, but the second FIFO (FIFO 1) comes back empty. Maybe I need ADC1 acquisition to occur in it's own timed loop with the ADC1_clk driving it? Maybe the problem is in the Host VI where I signal for acquisition and then read from FIFO before FIFO1? I'm hoping someone can provide an example to save me compile time in trying to guess my way through it. There must be a lot of people using both inputs!
Chris
Attachments:
DualADCtarget.JPG ‏52 KB

Sorry. I reposted on the IF-RIO board.
Chris

Using NI PCI-5640R as Real-Time Spectrum Analyzer

Hi,
The code for NI PXIe-5641R Real-Time Spectrum Analyzer demo is posted HERE for LV 2009. I want to use the same code for NI PCI-5640R instead of NI PXIe-5641R. Since I am using a 5640R, I have changed the device in the project.
Can any one guide me what else changes I have to make in this Demo code so that I can use the same code for NI PCI-5640R
instead of NI PXIe-5641R?
Thanks and Regards,
Rashid
Solved!
Go to Solution.

Hi Eug,
It sounds to me like you need to go back and re-install support for LabVIEW 2009 and 2010 through the NI-RFSA driver. You can do this through Add/Remove Programs. Select National Instruments "Change/Remove" and when the pop up window comes up select NI-RFSA and select "Modify." This will re-load the installer for NI-RFSA and through there you can add/remove support for versions of LabVIEW. Make sure that LV 2009 and 2010(if you're using it) are selected.
As for your application, if I understand you correctly your setup goes something like PXI-5600»PXIe-5641R»PXI-5610 (»PXI-5690?). If you're just trying to acquire a signal on the 5641R and amplify it digitally before replaying it on the AO port, then you could try to use the example code "ni5640R Analog Input and Output" that is found here:
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\ni5640R\FPGA\PXIe-5641R\ni5640R Analog Input and Output\
as a base to follow, but you'll need to modify the code so that you're not providing the AO data from the host, instead you'll re-route the AI data on the FPGA through some amplification block and then feed that to the AO port. If you're including the 5600 and 5610 in this process, then that modified example will just need to include some code on the host to setup the 5600 for downconverter only mode and the 5610 for upconverter only mode. There are examples of this that you can find in their respective driver examples:
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\niRFSA\RFSA Downconverter with External Digitizer.vi
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\niRFSG\RFSG External AWG (5610).vi
The addition of these last two pieces of code will make this modified example look a lot like the code that NAyer linked above without the FFT processing.
I hope this helps.
Chris W

PCI-5640R for my thesis

Hi everyone!
First, I apologize for my english, but I'll do my best to be understood
So, I'm starting with my thesis that I have to defend at the end of this year, and my mentor(?) gave me this PCI-5640R card to explore. At this point I must say, that I'm totally rookie with this Even more, I don't even know how to explore it. OK, I installed card in my PC, installed LabVIEW, drivers for the PCI card etc. It gets complicated or frustrated when I try to run some demos - it has always some errors.I read "Gettting started" thing, but still no success A lot of "VIs" is missing while loading example.
All I have to do is to run some demos for PCI-5640R card that will demonstrate it's functions and capabilities. And my thesis is basically done...well, still have to dome reasearch on SDR, DPS, LabVIEW etc.
Any help, suggestions will be more then appreciated!
Best regards from Slovenia!
Senad

SenadMur wrote:
Hi everyone!
First, I apologize for my english, but I'll do my best to be understood
So, I'm starting with my thesis that I have to defend at the end of this year, and my mentor(?) gave me this PCI-5640R card to explore. At this point I must say, that I'm totally rookie with this Even more, I don't even know how to explore it. OK, I installed card in my PC, installed LabVIEW, drivers for the PCI card etc. It gets complicated or frustrated when I try to run some demos - it has always some errors.I read "Gettting started" thing, but still no success A lot of "VIs" is missing while loading example.
All I have to do is to run some demos for PCI-5640R card that will demonstrate it's functions and capabilities. And my thesis is basically done...well, still have to dome reasearch on SDR, DPS, LabVIEW etc.
Any help, suggestions will be more then appreciated!
Best regards from Slovenia!
Senad
Senad,
I think I could better asses what is going on if you tell me what software you are running.
Please tell me your:
Operating System Version?
Operating System 32 or 64bit?
LabVIEW version?
LabVIEW 32bit or 64bit?
Are you using LabVIEW FPGA?
NI-RIO Version?
NI-5640R Driver Version?
These National Instruments software versions can be found in Measurement and Automation Explorer with the exception of the NI-5640R Driver. The NI-5640R driver version can be found by going to control panel >> add/remove programs >> National Instruments Software.
Also, if you write down a few of the missing file names it might help me figure out what is missing.

Pci-5640R Config.ADC 0 Microport Address write error

I am trying to run the tutorial in the "Getting Started with the NI PCI-5640R IF Transceiver and the LabVIEW FPGA Module" document. I got everything set up, but when I run it, I get an error which says
"Error -61059 occurred at Read/Write Control:Config.ADC 0 Microport Address in Simple Spectrum Analyzer.lvlib:ni5640R ADC address_port_write.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC read_write.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC read_write (multi-byte).vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC write_register.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC 01 - Chip IO Access.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC Global.vi->Simple Spectrum Analyzer.lvlib:ni5640R ADC Default.vi->Simple Spectrum Analyzer (HOST).vi"
I can't figure out how to fix it.

It may be that the FPGA Refernce has not been binded. The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control. This is an option on the popup menu when clicking on the Open FPGA VI Reference VI. In some cases, it may already be selected in the popup menu. In this case, unselect the Bind to Typedef option. For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option. In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI. In some cases, I have to Save All, close the host VI and all subVIs. Then reopen the host VI. This has always working in all cases for me.
Jerry

Simulation mode for PCI-5640R

Hi,
I am evaluating whether to buy a PCI-5640R (or PXI-5641R) card for a project. I would like to prototype the code first to see if what I want to do would work. Is it possible to use the 5640R driver in simulation mode, without a physical card installed? M-series daq cards support this, is there similar support for 5640R / 5641R/
thanks in advance
greg

Hi Greg,
You can simulate the use of your IF Transceiver code before you make a decision on whether or not to purchase. There are a couple caveats though. First, you must have the NI-5640R driver installed in order to find that device as a simulated device. The other thing is that you'll need to have the LabVIEW FPGA module already purchased and installed. If neither of these are issues, then you are good to go for prototyping. I recently updated the instructions on how to set your IF-RIO FPGA project for simulation that you can find HERE.The updates that I made to include the IF-RIO may not be live yet, but should be up within the next day. Those instructions should get you rolling. Enjoy!
Chris W

Sharing an external sample clock between PCI-6722 and PCI-6602

I need PCI-6602 work with PCI-6722。6602 shares 6722’s ao/SampleClock as external clock and triggered by 6722’s ao/StartTrigger。The master device is 6722, which refered as Dev1, and the slave device is 6602, which refered as Dev2. A RTSI line is used to connect the two devices correctly.
I use C API to finish my program and my code is as follows:
//config 6722 analog out task
1、DAQmxCreateTask("NI6672", &hAOTask);
2、DAQmxCreateAOVoltageChan(hAOTask, "Dev1/ao0", "", -10.0, 10.0, DAQmx_Val_Volts, "" );
3、DAQmxCfgSampClkTiming(hAOTask, "", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
4、DAQmxWriteAnalogF64(hAOTask, 1000, 0, 10.0, DAQmx_Val_GroupByChannel, data, NULL, NULL);
//config 6602 counter task
5、DAQmxCreateTask("NI6602", &hCounterTask);
6、DAQmxCreateCICountEdgesChan(hCounterTask, "Dev2/ctr0", "", DAQmx_Val_Rising, 0, DAQmx_Val_CountUp);
//use /Dev1/ao/SampleClock for external clock
7、DAQmxCfgSampClkTiming(hCounterTask, "/Dev1/ao/SampleClock", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
//use /Dev1/ao/StartTrigger
8、DAQmxSetTrigAttribute (hCounterTask, DAQmx_ArmStartTrig_Type, DAQmx_Val_DigEdge);
9、DAQmxSetTrigAttribute (hCounterTask, DAQmx_DigEdge_ArmStartTrig_Src, "/Dev1/ao/StartTrigger");
10、DAQmxSetTrigAttribute (hCounterTask, DAQmx_DigEdge_ArmStartTrig_Edge, DAQmx_Val_Rising);
//start counter task first
11、DAQmxStartTask(hCounterTask);
//start 6722 task
12、DAQmxStartTask(hAOTask);
I run it on the MAX virtual Device, and the Step 11always returned -89120。
I try to slove this problem, so I change the Step 7, use /Dev2/PFI9 to instead of /Dev1/ao/SampleClock.
7、DAQmxCfgSampClkTiming(hCounterTask, "/Dev2/PFI9", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
The code runs well, but I don’t know which terminal is connected by /Dev2/PFI9. Does it connect to /Dev1/ao/SampleClock？
I use another API DAQmxConnectTerms to ensure that, I add a Step before Step 11.
DAQmxConnectTerms( "/Dev1/ao/SampleClock", "/Dev2/PFI9", DAQmx_Val_DoNotInvertPolarity );
The program also run well. But I am still not sure that 6602 is sharing /Dev1/ao/SampleClock。If not, which terminal of Dev1 is connected by /Dev2/PFI9?
Is my code right? If not, hwo to fix my code or supply some example for me? Thanks.

Hello Shokey,
From looking over your post, it looks like you want to program in C, using simulated instruments, a master/slave design with a PCI-6602 and PCI-6722. The PCI-6722 is the master device and the PCI-6602 is the slave device. In order to implement this with the real cards, you would need a RTSI cable between the 2 cards in order to pass the triggers and the sample clock. Unfortunately with simulated devices you can't implement this so parts of your code won't be able to work exactly like if you had the instrument.
If you did have the instrument, you can implement this by performing the following steps:
Master Device:
1.) Export the ao/SampleClock and ao/StartTrigger to a RTSI Line. (See DAQmx C Reference help for DAQmxExportSignal to export these)
Slave Device:
1.) Set the Sample clock and the trigger to the RTSI.
There is another forum that I think will help you out to implement this correctly. In this forum, the customer was trying to export a trigger through a RTSI and the problem he was experiencing was a broken RTSI cable. His code, he states, works. I hope this helps you with this and if you have any more questions, feel free to post.
Jim St
National Instruments
RF Product Support Engineer

Hardware Clocking Error PCI-5122

I tried to run the vi attached (which i've run many times before) and my computer bluescreen. When it rebooted, I could no longer use my PCI-5122 digitizer card. When I try to do a device test or device reset in MAX, it tells me that theres a hardware clocking error.. I was using an external trigger for the aquisition, but don't think I was using an external reference clock. Could someone help me fix this?
Thanks
NI Hardware: PXI-7853R, PCI-5122, PCI-6733, PXI-1036, PCI-MIO-16E-4, PCI-6110
Computer Hardware: Xeon Quad Core - 2.33 Ghz, 8 GB RAM
Software: Labview 2009, Labview FPGA 2009, Vista 64-bit, MAX 4.6, DAQmx 9.0, NI-SCOPE 3.5
Solved!
Go to Solution.
Attachments:
OPO Monitor.vi ‏53 KB

Hi,
This error may be the result of a hardware failure where the only
solution is a repair or replacement. There are however, some basic
troubleshooting steps that have been known to correct this issue
without a return.
Reboot the PC or PXI controller.
Try a different PCI or PXI slot.
Update the driver to the latest version.
If possible try the card on a different machine.
If these steps to not correct the issue then it is likely the
board requires repair which can be arranged by contacting National
Instruments Technical support (in france: 01 57 66 24 24).
Best regards,
Thomas B. | CLAD
National Instruments France
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Hardware clock in PCI-6052E

Is there any indication either it uses windows clock or DAQ STC built in timer.
my question is how we know that a normal
programme in labview is using which clock???

Dear Haider,
Since you are using AI Start, your analog input is hardware timed. This means that your data is read from the buffer at regular times. Everything else in your program is software timed. I know this because the software is doing the checking for the condition and the digital lines of the PCI-6052E can be output with hardware timing, but it involves using the an analog clock. For more information on this look at the examples in the Example Finder (LabVIEW help menu>>Find Examples) under Browse Hardware Input and Output>>Traditional DAQ>>Digital Input and Output>>E Series.
Have a great day!
Marni S.

Is there a common(or systematic) way of have IQ data interleaved and sent? (PCI 5640R)

Hi,
    Thanks for the help!
   I have a further question about the IQ data.
   I am trying to write my baseband output to the DAC_IQ channel. I have two questions:
   1. what is the representation of IQ interleaved data? I mean, how they are interleaved? What data type should I use to write to the DAC_IQ? I see in one of the example that the data is contained in a I16, then processed with x2^(-2). Does that mean the -32576/4, 32576/4 is actual the range of the input to the DAC_IQ?
   2. Is there a usual way of interleaving the IQ data? (In the FPGA rather than in the host). I saw how they use array to interleave the data in the host block diagram.
   Thanks a log.
David

Hi David
1. The representation of each I and Q sample is I16. But the data must be in the lower 14 bits for the 14 bit DACs. So, looking at an I16 number, the actual decimal data range will be from -8192 to +8192.
They are interleaved I and Q, over and over. This is so that the I is the first data point out of the FIFO for the DAC, which requires the I before the Q for every IQ pair. There is an example of this in the ni5640R IQ Output example. Actually a subVI of the host VI.
2. I’m not sure how to answer this one. It sort of depends on where the samples are coming from and how they are created / stored. In the same IQ Output example, the data is interleaved by reading each I or Q value out of a FIFO at a time. In the ni5640R Frequency Translation (FPGA).vi, the data is saved in a FIFO as U32, combining both the I and Q sample. When retrieved from the FIFO, the U32 sample is retrieved every other iteration of the loop. The data is split, and the Q is shifted to the next iteration to write to the DAC, preserving the order that I and Q samples must be written to the DAC.
Jerry

Using timer/counter with PCI-6221/USB-6210 to control timed-loop VI

Dear all,
I need to ask about two devices and one of their functionalities, PCI-6221 and USB-6210. For our NI-based system, we need to control some timings in a Timed-Loop vi, for that currently we are using PCI-6221 and we give external TTL signal (at 1 kHz) to it,
recenntly we need to make some changes and for that we found USB 6210 DAQ to be more suitable, but we need to clear ourselves on some specific things.
Can the counter/timers functions available in the either PCI 6221 or USB 6210 can be used to control the Timed-loop VI by giving external clock or by using their own internal clock source?
Although we are using external clock with the PCI 6221 but we want to know about the usage of their internal clock, also are controlling timed-loop also possible for USB-6210
Also... What if we use the RTOS, are they still able to control the timed-loop VI without giving any 'EXTERNAL CLOCK' and using the internal clock sources of the DAQs
Waiting for reply,
Bests,
RaJaf
Solved!
Go to Solution.

Ben,
I having read previous email which I send earlier with general overview, we discussed in more detail within our team and I am giviing the specific answers.
Please check in RED the most recent answers. Blue are the questions/suggestions by your side.
1.    Using Internal hardware clock of PCI-6221 would enable us get rid of external clock, but how to divert the internal hardware clock to the current settings. Any idea (can you provide us with some reference manul for otherwise). I mean is there some flag-bit etc. or VI
2.       Is it also meant that with the installation of RTOS the timed-loop can directly get the timing source from the internal hardware clock PCI-6221? --- How???
3.       In order to make desktop to work as RT system, what is the hardware (motherboard, processor, etc..) requirement? What are the LabVIEW modules (specific name) that needed to be installed? Our platform is LabVIEW 8.6. (Currently we have windows-7 with i7 core processor)
What kind of application are you intending for this system? ---- high-speed laser scanning system.
Are you most concerned about accuracy, speed, or responsiveness? To control the laser mirror scanner to move at 1 kHz or 2 kHz speed. On the other hands, using PCI-5105 (128 MB memory) as a DAQ for real-time/on-the-fly data processing.
Bests,
RAJAF

5640r programming

Hi,
I am using
ni5640R card in a PCI slot using API Interface (5640R instrument driver V1.2).I
am using LabVIEW 8.5.1 and PC is loaded with Windows XP.
I have the following doubts.
1. I tried to generate a
sine wave using API interface.I got the analog output and viewed the result in
an Anritsu spectrum analyser.I could observe the waveform from both analog
channels AO0 and AO1one at a time.I could also vary frequency and amplitude of
the sine wave.I want to monitor the digital data (before it gets up_converted
and analog converted) in the PC itself using PCI bus interface or modulation
toolkit(MT) .Please explain me how to achieve this.
2.Please explain how to access
(acquire) output of any digital blocks of the VI in the PC using LabVIEW or
MT.
3.It is also
found that LabVIEW FPGA module can be used instead of API.I am using NI LabVIEW
FPGA module V8.5.1.Though I tried to use this toolkit several times, I couldn't
make it functional.When FPGA module is used , 5640R card is not detecetd .But
when 5640 API is used, card is detected.Because card is not detected while using
FPGA module, I am not able to program or proceed further.We also have installed
the NI RIO software of version 2.4.When RIO is installed it shows a list of
hardware it support in which 5640R is not shown.When FPGA module is used , the
device list is same as that shown by RIO.(5640R is not found in that list also).
I came to know that the FPGA module works only with NI RIO V2.3.1. Is it so? Can
you tell me what is wrong and help me to use FPGA module for programming
5640R?
Please advise on this
Thanking You

Hi,
1. PCI-5640R has a 14bit DAC and hence the I,Q data sent to the DAC are represented by 14bits, which is basically x*2^(13).
2. http://decibel.ni.com/content/docs/DOC-1710 has some examples using MT and NI-5640R instrument drivers.
3. I guess, the issues is with the order of installation.
 a. install LV
 b. install LVFPGA
 c. install NI-5640R 1.2
After
installation if the PCI-5640R is not shown as the target, then run
<LabVIEW 8.5>\Targets\NI\FPGA\bin\lvfpga_make_resource_cache.exe
--Vinay

Clock of PCI 5640R

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