External Reference Clock on pci-5640R

Hi. I want to clock my IF-RIO 5640R board, with an external reference clock at 2MHz frequency and i would to generate a 200 MHz clock inside the board (as the vcxo).
If I set properly the parameters inside the "configuration timebase" vi, using the pll on the cdc7005, can i achieve this feature?
How can i do?
Thanks....

If you use the fixed-personality driver, and you are feeling a little bit brave, you should be able to use ni5640R Configure Timebase.vi. It can be found (at least on my computer) at:
C:\Program Files\National Instruments\LabVIEW 8.2\instr.lib\ni5640R\Driver\NI-5640R VIs
Leave the defaults as they are, except change as follows:
Ref Divider (M) = 2 (for 2 MHz)
SMB Ext Ref Enable = True
VCXO Control = PLL
CP Enable = True
That should be everything, to the best of my memory. You may have to enable the Invert CP bit.
Hope this helps,
Ed

Similar Messages

Clock of PCI 5640R

Hi!
 I got a little bit confused by the clock of PCI 5640R.
 What does "nominal frequency" which appears when I add a clock in in the Project Explorer mean?
 How does it come into play with the following equation?
 DAC__IQ_Clk = 2 × REFCLKDAC_ × Clock multiplierDAC_ / InterpolationDAC_
 Thanks!
Dayu

Hi Dayu
The "nominal frequency" field in the Project Explorer is basically a value that the Xilinx tools use to determine if the FPGA code will run on the FPGA. In the process of compiling the code, it will determine the maximum speeds that portions of the circuit will run at. Say you specific 75.0 MHz. If Xilinx thinks the circuit can run at 100 MHz, there are no problems, but if Xilinx thinks that the circuit’s maximum speed is ~70 MHz, it will fail.
You should only have to change this if your FPGA code can’t run at the default number and you want to clock the circuit at a much slower rate. Then put in a value higher than the rate you are going to clock it, and lower than what the Xilinx tools say is the maximum rate for your code.
This value does not really factor into the DAC__IQ_Clk equation, which is configured with the Clock and DAC configuration VIs.
Jerry

Using an external reference clock for counter measurements

Hi all,
I have several PXI chassis
configured for testing, each of which uses an NI-DAQ-6221 for
conducting period and frequency measurements among other things.
However each of my setups give me a slightly different reading when conducting identical measurements due to
the tolerance of the DAQ on board reference
clocks.
The chassis' have a 10MHz GPS calibrated reference fed into them via the reference input and this is connected to the backplane. I have tried and failed to try to route and use this as my reference
base for my counter measurements so that each of my cards will give me
the same reading every time. I have tried the routing method using the
DAQ connect terminals vi but could not get this to work. I have looked through the labview examples and cant find anything thta shows me what i need to do to take frequency and period measurments using my external reference as my base clock. There are some examples showing the use of the DAQmx timing vi set to sample clock mode which allows a clock source to be selected. However these examples are only for counting digital events and when i apply the same vi to a frequency or period measurement an error is thrown saying 'invalid timing type for this channel', 'you can select: implicit, on demand'.
I do not
understand the working of the DAQ hardware very well so was hoping
someone could help explain to me how to do this if it is even possible
or give me any guidance as to how else to overcome my problem. Any vis
showing how to use my external 10MHz reference
as the base clock for these kind of measurements would be greatly appreciated.
Regards,
Dan

Hi Dan,
Thanks for the reply. When trying to use the connect terminals i just tried connecting the PXI10 to the onboard clock in the hope that this would configure it to use the PXI10 signal to synchronise the onboard clocks via the PLL. Doing this didn't throw any errors as i recall, it just gave me a reading of infinity as it couldn't measure the signal.
I have actually just managed to successfully do what i wanted thanks to help from Rob at NI tech support UK. There is a DAQmx timing property node which allows you to choose a reference clock source. By using the PXI_Clk10 signal this makes the DAQ synchronise its reference clocks to this signal. I have included an image of the code i used to achieve this to take period measurements.
Here is a very useful link which Rob sent me which may be of help to anyone else with similar problems
http://zone.ni.com/devzone/cda/tut/p/id/3615
Best regards,
Dan.
Attachments:
ExtRef Source Image.jpg ‏105 KB

Sharing an external sample clock between PCI-6722 and PCI-6602

I need PCI-6602 work with PCI-6722。6602 shares 6722’s ao/SampleClock as external clock and triggered by 6722’s ao/StartTrigger。The master device is 6722, which refered as Dev1, and the slave device is 6602, which refered as Dev2. A RTSI line is used to connect the two devices correctly.
I use C API to finish my program and my code is as follows:
//config 6722 analog out task
1、DAQmxCreateTask("NI6672", &hAOTask);
2、DAQmxCreateAOVoltageChan(hAOTask, "Dev1/ao0", "", -10.0, 10.0, DAQmx_Val_Volts, "" );
3、DAQmxCfgSampClkTiming(hAOTask, "", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
4、DAQmxWriteAnalogF64(hAOTask, 1000, 0, 10.0, DAQmx_Val_GroupByChannel, data, NULL, NULL);
//config 6602 counter task
5、DAQmxCreateTask("NI6602", &hCounterTask);
6、DAQmxCreateCICountEdgesChan(hCounterTask, "Dev2/ctr0", "", DAQmx_Val_Rising, 0, DAQmx_Val_CountUp);
//use /Dev1/ao/SampleClock for external clock
7、DAQmxCfgSampClkTiming(hCounterTask, "/Dev1/ao/SampleClock", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
//use /Dev1/ao/StartTrigger
8、DAQmxSetTrigAttribute (hCounterTask, DAQmx_ArmStartTrig_Type, DAQmx_Val_DigEdge);
9、DAQmxSetTrigAttribute (hCounterTask, DAQmx_DigEdge_ArmStartTrig_Src, "/Dev1/ao/StartTrigger");
10、DAQmxSetTrigAttribute (hCounterTask, DAQmx_DigEdge_ArmStartTrig_Edge, DAQmx_Val_Rising);
//start counter task first
11、DAQmxStartTask(hCounterTask);
//start 6722 task
12、DAQmxStartTask(hAOTask);
I run it on the MAX virtual Device, and the Step 11always returned -89120。
I try to slove this problem, so I change the Step 7, use /Dev2/PFI9 to instead of /Dev1/ao/SampleClock.
7、DAQmxCfgSampClkTiming(hCounterTask, "/Dev2/PFI9", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
The code runs well, but I don’t know which terminal is connected by /Dev2/PFI9. Does it connect to /Dev1/ao/SampleClock？
I use another API DAQmxConnectTerms to ensure that, I add a Step before Step 11.
DAQmxConnectTerms( "/Dev1/ao/SampleClock", "/Dev2/PFI9", DAQmx_Val_DoNotInvertPolarity );
The program also run well. But I am still not sure that 6602 is sharing /Dev1/ao/SampleClock。If not, which terminal of Dev1 is connected by /Dev2/PFI9?
Is my code right? If not, hwo to fix my code or supply some example for me? Thanks.

Hello Shokey,
From looking over your post, it looks like you want to program in C, using simulated instruments, a master/slave design with a PCI-6602 and PCI-6722. The PCI-6722 is the master device and the PCI-6602 is the slave device. In order to implement this with the real cards, you would need a RTSI cable between the 2 cards in order to pass the triggers and the sample clock. Unfortunately with simulated devices you can't implement this so parts of your code won't be able to work exactly like if you had the instrument.
If you did have the instrument, you can implement this by performing the following steps:
Master Device:
1.) Export the ao/SampleClock and ao/StartTrigger to a RTSI Line. (See DAQmx C Reference help for DAQmxExportSignal to export these)
Slave Device:
1.) Set the Sample clock and the trigger to the RTSI.
There is another forum that I think will help you out to implement this correctly. In this forum, the customer was trying to export a trigger through a RTSI and the problem he was experiencing was a broken RTSI cable. His code, he states, works. I hope this helps you with this and if you have any more questions, feel free to post.
Jim St
National Instruments
RF Product Support Engineer

Hardware Clocking Error PCI-5122

I tried to run the vi attached (which i've run many times before) and my computer bluescreen. When it rebooted, I could no longer use my PCI-5122 digitizer card. When I try to do a device test or device reset in MAX, it tells me that theres a hardware clocking error.. I was using an external trigger for the aquisition, but don't think I was using an external reference clock. Could someone help me fix this?
Thanks
NI Hardware: PXI-7853R, PCI-5122, PCI-6733, PXI-1036, PCI-MIO-16E-4, PCI-6110
Computer Hardware: Xeon Quad Core - 2.33 Ghz, 8 GB RAM
Software: Labview 2009, Labview FPGA 2009, Vista 64-bit, MAX 4.6, DAQmx 9.0, NI-SCOPE 3.5
Solved!
Go to Solution.
Attachments:
OPO Monitor.vi ‏53 KB

Hi,
This error may be the result of a hardware failure where the only
solution is a repair or replacement. There are however, some basic
troubleshooting steps that have been known to correct this issue
without a return.
Reboot the PC or PXI controller.
Try a different PCI or PXI slot.
Update the driver to the latest version.
If possible try the card on a different machine.
If these steps to not correct the issue then it is likely the
board requires repair which can be arranged by contacting National
Instruments Technical support (in france: 01 57 66 24 24).
Best regards,
Thomas B. | CLAD
National Instruments France
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5600 Downconverter : 10 MHz Reference CLOCK

Hi RFSA Guys,
Is it possible to vary the 10 MHz Reference Clock and use it ... for demodulation of RF Signals
to a new value ... lets say 9.9992 MHz ?
If this is possible, upto what resolution can I vary the clock..
Can I vary it terms of 0.1 Hz or 0.01 Hz.. Is the 10 MHz Reference Clock truly that stable ?
I have a competitor clock which is stable upto 0.01 Hz... but not in PXI Form.
If this is not possible, Can anyone suggest a PXI Version of a Variable Stable External Reference Clock ?
Basically, I am looking at varying the Reference Clock to vary my Symbol rate for a Device Under Test.
Thanks for your help..
Dharmendra

Dharmendra,
You might also run into problems when the downconverter tries to phase-lock to that reference clock, since it's expecting 10 MHz. Can you tell us a bit more about what you're trying to do? There might be a different way to accomplish it. Thanks!
Chad B. » National Instruments » ni.com

External reference for USB 5132

Hello,
I have a couple (hopefully) general questions about using an external reference clock on our USB 5132 digitizer. We want to lock it to the other oscillators in our system, all of which are presently locked to one 10 MHz reference. If I connect our existing 10 MHz reference to the PFI1 input, my questions are:
1. Is the 5132 now locked to our system? Or, do we need to specifiy in the setup software that we want to override the 5132's internal reference and rely entirely our external reference?
2. In order to have the best possible lock, do we need to tell the 5132 to sample at a frequency that is evenly divisible by 10 MHz (e.g. 20 MHz, 10 MHz, 5 MHz, 2 MHz, etc.)? Similarly, are we worse off if we want to sample at say, 13 MHz?
Thanks for any thoughts.
Best regards,
Penny
Solved!
Go to Solution.

Hello Penny,
1. Yes the 5132 is locked to your reference system 10MHz clock (with some offset due to delay in the time it takes to transmit the clock signal from your system to this USB device) if you selected the PFI line as the source of an external timebase. Please take a look at the following example Help>>Find Examples>>Hardware Input and Output>> Modular Instruments>>NI-Scope>>Features>> niScope EX External Clocking.vi.
2. No, although I would expect that if you enter in 13MHz and your device was not capable of doing this it would coerce it to the closest value. I would suspect that only integer divide downs from the clock in question are valid such that 12. 5MHz is the value it would coerce to if you were to request a 13MHz value (with a 50MHzexternal clock). The 5132 can not do RIS so sampling at 20MHz with a 10MHz SampleClock Timebase Source is not feasable.
Regards,
Izzy O.
Applications Engineer
National Instruments
www.ni.com/support

NI5112 PFI Reference Clock Input Problem

I'm writing C code to use an NI5112 O-Scope card as a digitizer and I would like to synchronize it with an HP 8648C signal generator (which has the high-stability timebase option) through PFI1. I want to use the signal generator for the reference clock as the NI5112 samples about 40 Hz high at 5 MSamples/s and because I need the two to drift together. When I use the signal generator as reference clock the result is a very "noisy", i.e. with an input sine wave the FFT is noisy, and I the timing is too bad for processing input GPS signals (which have stringent timing requirements). If I use an Agilent 33120A function generator as the reference clock, I get better results, but GPS processing is still compromised. When not using a
n external reference everything looks clean and works fine except for 40 Hz error in the sample rate. The reference outputs from both the 8648C and 33120A work fine with each other and look good and clean with the o-scope, so I can't figure what the problem is. Maybe the card is just extremely picky about external reference clocks. The function call I'm using to initialize this is:
handleErr(niScope_ConfigureClock(vi, NISCOPE_VAL_PFI_1,
NISCOPE_VAL_NO_SOURCE,
NISCOPE_VAL_NO_SOURCE,
NISCOPE_VAL_FALSE));
The program runs normally with no errors, it's just that the results are bad. Any help would be appreciated.

Hello,
If the data that you are acquiring is very noisy, I would start getting suspicious about the input impedance (1MOhm or 50Ohm). Does the impedance of the signal generator match the scope's? How does your signal look in the Scope Soft fron Panel? Does it make a difference if you use the internal clock?
Another thing that I would consider is the following parameter from the niScope_ConfigureClock function: NISCOPE_ATTR_CLOCK_SYNC_PULSE_SOURCE. In order to synchronize your arb to the scope, not only they need to share the same clock (10MHz), but also the slave receives this sync pulse from the master. In you application, if the signal generator has the ability to send a sync pulse, you can route that signal through PFI2 to ensure synchronization.
Hope this helps. Good luck with your application!
Annette Perez

FPGA Base Clocks PCI-5640R

Hi,
 I am using NI PCI-5640R. Following FPGA Base Clocks are available to me:
(1) Configuration_Clk
(2) RTSI_Ref_Clk
(3) DAC_0_IQ_Clk
(4) DAC_1_IQ_Clk
(5) ADC_0_Port_A_Clk
(6) ADC_1_Port_A_Clk
Can anyone help me with brief descriptions of each clock? When these clocks are to be used?
Kindly send me some URL links where I can find details about the usage of these clocks?
Thanks and Regards,
Rashid
Solved!
Go to Solution.

Hello Rashid,
(1) Configuration_Clk - This is 20MHz onboard clock, which runs independently of the other clocks. The role of the 20MHz configuration_clk is to provide a fixed frequecny configuration clock that is use by STC2 ASCI for PCI-DMA operations. Also this clock is not synchronized to the 200MHz VCXO or to the external clock
(2) RTSI_Ref_Clk - This is a device reference clock derived from 200MHz internal VCXO, by setting the dividing factor ranging from 1,2,4,8 and 16.
The I/Q clocks are the signals that indicate the rate of the baseband data. These clocks indicate the rate of the data before the digital upconversion in DAC and the rate of the data after the digital downconversion for ADC. They are described as below.
(3) DAC_0_IQ_Clk and (4) DAC_1_IQ_Clk -
 DAC__IQ_Clk = 2 × REFCLKDAC_ × Clock multiplierDAC_ / InterpolationDAC_
where
REFCLKDAC_ is the specified device reference clock / N2 or 3 CDC. Specify the divisor using the ni5640R CDC Program VI.
Clock multiplierDAC_(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R DAC Program VI.
InterpolationDAC_ is the hardware interpolation rate determined by the DAC fixed 4× interpolator times a programmable 2× to 63× CIC interpolating filter. The programmable CIC interpolator can be configured using the ni5640R DAC Profile VI.
(5) ADC_0_Port_A_Clk and (6) ADC_1_Port_A_Clk -
 ADC__Port_A_Clk = ENCADC_ × Clock multiplierADC_ / (Predivide FactorADC_ × DecimationADC_)
where
ENCADC_ is the device reference clock / N0 or 1 CDC. Specify the divisor using the ni5640R Configure Timebase VI.
Clock multiplierADC_(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R Input Port VI.
Predivide FactorADC_ (N) is equal to 1, 2, 4, or 8. Configure the predivide factor using the ni5640R Input Port VI.
DecimationADC_ is the decimation factor for a particular channel in the ADC. Decimation is performed in various filters throughout the processing channel. Each channel includes one CIC filter (decimates by 1 to 32), two FIR-HB filters (each decimates by 2), one DRC filter (decimates by 1 to 16) and one CRCF filter (decimates by 1 to 16). Configure all these filters using the ni5640R ADC Configure DDC VI.
The figure below shows how all the above clocks are derived
Thanks
NI-khil

How to get 10 MHz reference clock out of PCI-5922

Hi,
I am evaluating PCI-5922 for the my application.
In my application, PCI-5922 will get signal from agilent 33250 function generator and both instruments will be triggered at the same time with the same trigger signal.
Is there any way to take out reference clock (10 MHz) out of PCI-5922? If that is possible, synchronizing can be easier.
I am expecting to have answers from experts!
Zeehoon
Solved!
Go to Solution.

Hi Zeehoon,
There are two steps to export the 10MHz reference clock out of the PCI-5922.
1)Specify the reference clock source (to use the internal reference select "no source")
2)Specify the reference clock output (a list of valid terminals can be found in the PCI-5922 Routing Matrix inside the High Speed Digitizers Help)
Here is a LabVIEW snippet showing the clock exported to PFI 1:
-Jennifer O.
Message Edited by Jennifer O on 09-16-2009 04:00 PM
Attachments:
ExportReference.JPG ‏11 KB

Could I use PCI-6601 to generate a 200Hz clock based on a external 40kHz clock?

Could I use PCI-6601 to generate a 200Hz clock based on a external 40kHz clock?
That means I want to use PCI-6601 as a frequency divider. (40KHz->200Hz)
Is it possible? Is there any example I can refer to?

1. Yes it's definitely possible to make such a frequency divider.
2. Here are a couple links that may help:
http://forums.ni.com/ni/board/message?board.id=40&message.id=3607&requireLogin=False
http://forums.ni.com/ni/board/message?board.id=170&message.id=78359#M78359
http://forums.ni.com/ni/board/message?board.id=40&message.id=4232&requireLogin=False
-Kevin P.

Multiple issues with PCI-5640R FPGA: DAC and Strange Execution at Host

We are working on a communications systems project using the PCI-5640R
IF-RIO transceiver and the FPGA module. At the FPGA, a sequence of bits are
being modulated through multiplication with the sine wave generator. The
next step is to take the modulated sinusoidal signal and send it through the
DAC. Throughout this project, we have been using the Analog Input and Output
example project from Getting Started with the 5640-R IF... as a template
to build this project. There are, however, several issues/questions we
have. Attached are the HOST and FPGA vis that we are working with.
1. The host only runs every other time. At the host (BPSK_TX(HOST).VI, the execution gets
halted for an infinite period of time at one of the FIFOs until 'stop' is
hit. But then at the subsequent execution, the host completes execution
of the program. In other words, the host is only receiving data from the
FPGA every second time it is run. Why is this happening? Are we missing
something at the host or FPGA VI?
2. How exactly do we send our own digitized signal through
the DAC? As seen in one of the FPGA VIs, we have tried modfiying the
output section of the FPGA VI in the Analog Input and Output project in which
the FPGA reads from the FIFO. In our case, we are modulating the signal
in a separate section, writing it to a target-scoped FIFO and then reading from
that FIFO and processing the data as in the example. This modified FPGA
vi is "BPSK_TX(FPGA).VI)
Unfotunately, we are not observing anything at an oscilloscope
connected to the transceiver. Even when we try to pass in a
"custom" signal at the HOST we have no luck observing anything
coherent. As seen in the bare_sine_wave_test (FPGA).vi, we have
attempted a relatively simple way of sending a signal through the DAC, yet
still no luck. I am guessing that this is related to issue #1.
On a related note, when
receiving the signal and running it through the ADC, what steps are
necessary? Can one assume that it is
similar to the FPGA.VI in the analog input and output example?
3. How do for loops and while loops synchronize with timed loops
and frames in the FPGA? In the FPGA we are using a for loop to
modulate the signal because the sine wave generator cannot be contained within
a timed loop on the FPGA. This will be important to us because at the
receiver we will need to know the symbol rate in order to recover the signal.
I would sincerely appreciate any feedback or help that can be provided
on this,
Attachments:
BPSK_TX(FPGA).vi ‏152 KB
BPSK_TX(HOST).vi ‏257 KB
bare_sine_wave_test (HOST).vi ‏135 KB

It may be that the FPGA Refernce has not been binded. The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control. This is an option on the popup menu when clicking on the Open FPGA VI Reference VI. In some cases, it may already be selected in the popup menu. In this case, unselect the Bind to Typedef option. For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option. In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI. In some cases, I have to Save All, close the host VI and all subVIs. Then reopen the host VI. This has always working in all cases for me.
Jerry

Err. -200303: External sample clock source...

Dear Readers
I'm using Ni-DAQmx 8 and have a PCIe-6259 card.
I wrote the following code (in VC++ 6).
int main(int argc, char* argv[])
    int32       error=0;
    TaskHandle taskHandle=0;
    uInt8      data[10]={1,2,4,8,16,32,64,128,256,0xFFFFFFFF};
    char        errBuff[2048]={'\0'};
    (error = DAQmxCreateTask("",&taskHandle));
    (error = DAQmxCreateDOChan(taskHandle,"Dev1/port0","",DAQmx_Val_ChanForAllLines));
    (error = DAQmxCfgSampClkTiming(taskHandle,NULL,1000.0,DAQmx_Val_Rising,DAQmx_Val_ContSamps,1000));
    error = DAQmxWriteRaw(taskHandle, 10, true, 10.0, data, NULL, NULL);
        if( DAQmxFailed(error) )
        DAQmxGetExtendedErrorInfo(errBuff,2048);
    ERROR: -200303: External sample clock source must be specified for this application
    error = DAQmxStartTask(taskHandle);
I See no output on the oscilloscope.
I tried to put in several values for ClockSource in DAQmxCfgSampClkTiming like Dev1/PFI0, .... - but it never worked.
Could anyone please help me?
Thanks...
Pascal

Hi Robert
Do yo mean something like this:
int main(int argc, char* argv[])
    int32       error=0;
    TaskHandle digiTaskHandle = 0;
    TaskHandle aiTaskHandle = 0;
    uInt32      data[10]={0xFFFFFFFF,2,4,8,16,32,64,128,256,0xFFFFFFFF};
    float64        dummyBuffer[10];
    char        errBuff[4096]={'\0'};
    error = DAQmxCreateTask("",&digiTaskHandle);
    error = DAQmxCreateTask("",&aiTaskHandle);
    error = DAQmxCreateDOChan(digiTaskHandle,"Dev1/port0","",DAQmx_Val_ChanForAllLines);
    error = DAQmxCreateAIVoltageChan(aiTaskHandle, "Dev1/ai0", "", DAQmx_Val_RSE, -5.0, 5.0, DAQmx_Val_Volts, "");
    error = DAQmxCfgSampClkTiming(aiTaskHandle, "/Dev1/ai/SampleClock", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
    error = DAQmxCfgSampClkTiming(digiTaskHandle,"/Dev1/ai/SampleClock" ,1000.0,DAQmx_Val_Rising,DAQmx_Val_ContSamps,1000);
    error = DAQmxStartTask(aiTaskHandle);
ERROR:
"An attempt has been made to perform a route when the source and the destination are the same terminal.
In many cases, such as when configuring an external clock or a counter source, you must select a PFI, PXI Trigger, or RTSI line as the sou"
//    error = DAQmxReadAnalogF64(aiTaskHandle, 10, 20.0, DAQmx_Val_GroupByChannel, dummyBuffer, 10, NULL, NULL);
    if( DAQmxFailed(error) )
      DAQmxGetExtendedErrorInfo(errBuff,4096);
    error = DAQmxWriteRaw(digiTaskHandle, 10, true, 10.0, data, NULL, NULL);
    //error = DAQmxStartTask(aiTaskHandle);
    if( DAQmxFailed(error) )
      DAQmxGetExtendedErrorInfo(errBuff,2048);
    return 0;
Could you please explain me how to do it right?
Pascal

Can buffered digital edge detection only be performed using an external sample clock?

I am working on an application where I need to measure the speed (rpm) of a motor as it starts up using the output of its built in hall effect sensor. The sensor should output 2 pulses per revolution of the motor. My plan is to count the pulses from when the counter (counter 1) is armed to when it is up to speed. Looking at the M series manual, the CVI (v8.5.1) help, and the examples it appears that this can only be done using an external sample clock. Is there a way to route an internal sample clock to the appropriate terminal on the counter so that I do not need to add additional hardware?
I am currently using a PCI-6289, but the final application will use a CDaq-9188 chassis (using one of the the built in 32-bit counters).
Thank you for your assistance.

Thank you for your input.
However, I did forget to mention one detail of the application. I need to buffer the edge counts so that I can graph the speed of the motor as it starts up. I need to be able to acquire the edge counts at reqular intervals so that I can determine how fast the motor was rotating at each point. So far I have not been able to find an example of doing this without and external sample clock. As I mentioned, in the final application I will be using the 32-bit counters on a CDAQ-9188 chassis. The only thing I can think of at this point is to generate a pulse out of the second counter and use that as the sample clock. Will this work?

Using NI PCI-5640R as Real-Time Spectrum Analyzer

Hi,
The code for NI PXIe-5641R Real-Time Spectrum Analyzer demo is posted HERE for LV 2009. I want to use the same code for NI PCI-5640R instead of NI PXIe-5641R. Since I am using a 5640R, I have changed the device in the project.
Can any one guide me what else changes I have to make in this Demo code so that I can use the same code for NI PCI-5640R
instead of NI PXIe-5641R?
Thanks and Regards,
Rashid
Solved!
Go to Solution.

Hi Eug,
It sounds to me like you need to go back and re-install support for LabVIEW 2009 and 2010 through the NI-RFSA driver. You can do this through Add/Remove Programs. Select National Instruments "Change/Remove" and when the pop up window comes up select NI-RFSA and select "Modify." This will re-load the installer for NI-RFSA and through there you can add/remove support for versions of LabVIEW. Make sure that LV 2009 and 2010(if you're using it) are selected.
As for your application, if I understand you correctly your setup goes something like PXI-5600»PXIe-5641R»PXI-5610 (»PXI-5690?). If you're just trying to acquire a signal on the 5641R and amplify it digitally before replaying it on the AO port, then you could try to use the example code "ni5640R Analog Input and Output" that is found here:
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\ni5640R\FPGA\PXIe-5641R\ni5640R Analog Input and Output\
as a base to follow, but you'll need to modify the code so that you're not providing the AO data from the host, instead you'll re-route the AI data on the FPGA through some amplification block and then feed that to the AO port. If you're including the 5600 and 5610 in this process, then that modified example will just need to include some code on the host to setup the 5600 for downconverter only mode and the 5610 for upconverter only mode. There are examples of this that you can find in their respective driver examples:
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\niRFSA\RFSA Downconverter with External Digitizer.vi
C:\Program Files\National Instruments\LabVIEW 2009\examples\instr\niRFSG\RFSG External AWG (5610).vi
The addition of these last two pieces of code will make this modified example look a lot like the code that NAyer linked above without the FFT processing.
I hope this helps.
Chris W

External Reference Clock on pci-5640R

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