Compiling errors under LabVIEW FPGA v1.1

Problems compiling any designs to target PXI-7831R.
Compile Server v1.1 starts but fails after 5 seconds. Details window reports "#SERVER ERROR: Error while Compiling #"
I have checked the configuration and it points to the correct directories. I have removed and reinstalled Labview 7.1 and FPGA module 1.1, but the problem persists.
The design compiles correctly on another machine so it appears to be related to the software installation on this machine.
I have attached the xflow.log report from the srvrTemp directory for this design. It is complaining that it cannot find a VHDL file : nirvi_zerodelayer.vhd
The VHDL file does exist in the clntTmp directory for this design but not in the srvrTmp directory.

Hi, this happened to me regularly. What I use to do is to delete the whole content of "C:\NIFPGA11\clntTmp"
and "C:\NIFPGA11\srvrTmp\localhost". Also, I've noticed that compilation may not fail if I click run instead of build when the target is "FPGA Device (PXI-7831R) <compile only>"... stange!
hope this helps!

Similar Messages

Compile Error When Running FPGA VI

Primary Software: LabVIEW Modules>>LabVIEW FPGA Module
Software Version: 8.6.1
I have an FPGA VI which uses 3 sin_generators. When I compile the VI, the compiler returns the error
Sine_geneartot_rvi_FPGA_main_vi_FPGA compile copy 1_vi_intance
Line_21 width mismatch. Expected width 8,actual width is 16 for dimension 1 of lutoutERROR:Xflow – Program xst returned error code 6. Aborting flow execution.
Why does this occur? How can I prevent it?

Could you please post your VI here?
Thanks,
Christian

Forms compilation Errors under Linux

Hello,
I have a main form called Tbdoctrk.fmb.
This forms compiles and runs perfectly through Oracle 9i iDS.
When transfering the fmb file under Linux, and attempting to recompile using the f90genm.sh utility, I get the following compilation errors:
FRM-18108: Failed to load the following objects.
FRM-30436: Parent window not specified for canvas.View Canvas H_TOOLBAR
FRM-30041: Position of item places it off of canvas.
Item: BUTTON_HELP
Block: VARIABLE
Form: TBDOCTRK
FRM: Unable to adjust form for output.
====
I noticed that most of the object that failed to load (1 data block object, 1 canvas and a number of property classes and visual attributes) are contained in a file called TOOLBAR.fmb.
The TOOLBAR.fmb file compiles without errors under Linux/WIndows + is located in the same folder as the Tbdoctrk.fmb file.
1) How can I resolve this issue ?
PT
PS: I tried renaming the fmb files to upper/lower case without success.

Hello,
My main form called Tbdoctrk.fmb in turn calls a form called Pre_bord.fmb in a Program Unit.
Most but not all Class and Value Attributes are included in a file called toolbar.fmb. I did not find any specific reference to the toolbar.fmb file.
However, at compile time, I find that those objects are not loaded.
1) In what part of the main form Tbdoctrk.fmb should I find any such reference to the toolbar.fmb file ?
2) How should I create those symbolic links under Linux ?
PT

XMP Toolkit compilation error under win32 + recent VC editions

Hi all,
I just downloaded the XMP plugin and tried to compile it under win xp with VC9 (express edition).
I get the following error a few times:
C:\Program Files\Microsoft Visual Studio 9.0\VC\include\stdio.h(358) : error C3163: '_vsnprintf': attributes inconsistent with previous declaration
1> C:\Program Files\Microsoft Visual Studio 9.0\VC\include\stdio.h(350) : see declaration of '_vsnprintf'
I'm not expert of win32 and/or VC environment, but I find quite strange that there is an error in stdio.h.
Maybe some duplicate definition in XMP toolkit? Any hint?
Thanks a lot,
Roberto

Thanks a lot!
Regards,
Roberto
2010/5/6 Joerg Ehrlich <[email protected]>:
Hi Roberto,
>
sorry for the late reply.
Unfortunately the compilation error is due to a certain combination of the VS compiler and the third-party ZLib library used in XMPFiles.
When compiling XMPFiles with the new Visual Studio 2008, certain definitions in the version 1.2.3 of ZLib collide with definitions in the CRT used in VS2008.
The solution is to get the latest version of ZLib which is 1.2.5. But you also need to adjust the XMPFiles VS project a little bit.
In that VS project you need to remove the file "gzio.c" from this folder: XMPFiles/Source Files/Third Party/zlib.
With those two changes, the toolkit should compile.
But you could also wait for the CS5 SDK which is about to be released pretty soon, which has this fixed as well.
>
If you have further questions, please let me know.
Kind Regards
Jörg
Adobe XMP
>

Compile error of LabVIEW C code in vxworks 5.5.1/tornado 2.2.1

Ladies and Gentlemen,
I am trying to run a LabVIEW-generated C code {Calling a LabVIEW-built DLL in C to Acquire, Analyze, and Present Data (http://zone.ni.com/devzone/cda/epd/p/id/1515)} in VxWorks 5.5.1. However, I have the following errors in using Tornado 2.2.1 to compile:
vxrm *.o *.rpo ctdt.c symTbl.c vxApp* *.out *.pl
vxrm ..\prjComps.h ..\prjParams.h ..\prjConfig.c ..\linkSyms.c
vxrm ..\libs.nm ..\libs.size
ccsimpc -g -mpentium -ansi -fno-builtin -fno-defer-pop -I. -IC:\WindRiver\Tor2.2-PPC\targe
t\h\ -DCPU=SIMNT -DTOOL_FAMILY=gnu -DTOOL=gnu -Wall -c ..\callLVDLL.c
In file included from ..\extcode.h:14,
                 from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\platdefines.h:308: #error
..\platdefines.h:339: parse error
In file included from ..\extcode.h:15,
                 from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\fundtypes.h:17: parse error
..\fundtypes.h:43: stdint.h: No such file or directory
In file included from ..\fundtypes.h:61,
                 from ..\extcode.h:15,
                 from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\lv_prolog.h:37: parse error
In file included from ..\extcode.h:15,
                 from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\fundtypes.h:157: parse error
In file included from ..\fundtypes.h:252,
                 from ..\extcode.h:15,
                 from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\lv_epilog.h:17: parse error
In file included from ..\extcode.h:15,
                 from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\fundtypes.h:361: parse error
..\fundtypes.h:370: parse error
..\fundtypes.h:386: parse error
In file included from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\extcode.h:40: parse error
..\extcode.h:49: parse error
..\extcode.h:57: parse error
In file included from ..\extcode.h:116,
                 from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\lv_prolog.h:37: parse error
In file included from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\extcode.h:526: parse error
..\extcode.h:959: parse error
In file included from ..\extcode.h:1080,
                 from ..\LV_AAP.h:1,
                 from ..\callLVDLL.c:23:
..\lv_epilog.h:17: parse error
make: *** [callLVDLL.o] Error 0x1
Done.
I would appreciate your help in this matter. "LV_AAP.h" and "callLVDLL.c" will be furnished upon request OR you can download from
http://zone.ni.com/devzone/cda/epd/p/id/1515
The rest of the header files are in my directory:
C:\Program Files\National Instruments\LabVIEW 2010\cintools
Regards,
Chi

Hello Che,
Thanks for your response. My real-time target hardware is MVME5100. However, at present I want to see whether a C code {see the attached callLVDLL.c} generated from LabVIEW can be compiled in VxWorks 5.5.1/Tornado 2.2.1. The reason why I am using an old version of VxWorks/Tornado is my company is transitioning to NI PXIe hardwares and LabVIEW software, and phasing out all of VME boards {Power 4e, Power 7e, and MVME5100}.
All of header files are included in Tornado 2.2.1. If you are correct about compiling an .out file using Tornado 2.2.1, then what changes should be made to "callLVDLL.c" for a successful Tornado compilation?
The documentation you recommended refers to a newer version of VxWorks/Tornado, which I do not think is helpful.
Thanks for your help,
Chi
Attachments:
callLVDLL.c ‏3 KB
LV_AAP.h ‏1 KB

"LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD

The compilation of my labview fpga vi fails with the error message "LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD".
In the 'final timing (place and route)' report, the requested frequencies are all below the maximum frequencies and the compilation error message is only displayed at the very end on the 'summary' page.
I tried to optimize my labview fpga vi with pipelining, but had no success.
Can anybody offer some advice on how to debug fpga code with this error? Is this really a timing error or something else?
Software:
Labview 2011, fpga 2011, xilinx tools 12.4 sp1
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
The Xilinx log of the compilation run is attached.
Also, this issue was already discussed in this thread ~6 months ago, but no satisfying answer was offered so far...
Thanks,
Fabrizio
Attachments:
xilinxlogc.txt ‏2313 KB

Hi Kyle,
the problem is: I have one computer which compiles the VI successfully and a second one which shows that error. Both use the same software setup (LV2011SP1+RT+FPGA from DS2012-01). Both use the same project file - atleast SVN shows no difference.
- You can have one FPGA VI where one computer is compiling successful and a second one complains. (Btw. I have a SRQ running in Germany on this topic.)
- More problems: After successful compiling on first computer and transferring all to second computer (using SVN, including the full project folder with all files like bitfiles, lvproj, and everything) the second computer is unable to start the RT executable due to error "FPGA VI needs to recompile". Solution so far: Call the FPGA-OpenReference with the bitfile instead of the VI (as I used to do until now)...
- More problems: After modifying the FPGA-OpenReference to use the bitfile (on the 2nd computer) and transferring all the files back to the 1st computer (using SVN as before, including the whole project) the 1st computer complains: FPGA-OpenReference is creating a different reference than is used in the VI. So what happens here? On one computer my VI is ok, the reference is typed correctly. Transferring all the files to a different computer the VI isn't ok anymore due to changes of the reference??? You know: all files are the same: lvproj, FPGA bitfile didn't change, cRIO reference didn't change...
All those problems didn't occur on my RT-FPGA projects in LV2010SP1. I'm not pleased...
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred

Hi,
I am trying to build a LabView FPGA VI. During compilation, I always get error stating "LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support". At the time, comiplation process is almost at the end. "Final Timing (place and route)" shows as completed. When Checked the Xilinx log session, at the end it states that " Process "Generate Programming File" completed successfully". However, I do not see any generated bitfile.
When clicked on error details, it shows following:
LabVIEW: An unknown error occurred.
Error -2629 occurred at Error occurred while loading XML string. Invoke Node in niFpgaXml_PrettyPrint.vi->niFpgaWriteBitfileXml_Core.vi->niFpgaCompileWorker_CreateBitfile.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:6460001
Possible reason(s):
LabVIEW: An unknown error occurred.
I tried multiple times but so far no luck to generate bitfile for this VI. What could be wrong here?
I am using Labview 2013

Hi Mark,
Here is the device utilization Summary. My development system is running with Windows-7 (32 bit) with 3GB RAM and Labview 2013.
Device Utilization
Total Slices: 90.0% (11970 out of 13300)
Slice Registers: 40.7% (43258 out of 106400)
Slice LUTs: 71.6% (38103 out of 53200)
DSP48s: 1.4% (3 out of 220)
Block RAMs: 22.1% (31 out of 140)
Timing
40 MHz Onboard Clock
: 40.00 MHz (57.90 MHz maximum)
80MHz (Used by non-diagram components)
: 80.00 MHz (100.19 MHz maximum)
--WillsG

FlexRIO DRAM problem in Labview FPGA 2010

Hello,
I am just switching from Labview FPGA 2009 to Labview FPGA 2010 and I am having compilation problems with very simple projects that shouldn't fail to compile.
I am using a FlexRIO 7965R board as a target. Initially, I just wanted to recompile a project that was working fine under Labview FPGA 2009. When it failed, I drastically
simplified it to isolate the source of error. I ended up with what is attached. In this very simple VI I just write some values into DRAM banks in one timed loop, read them out in another and send them through a Target to Host DMA FIFO. Both loops are quite slow running at only 40 MHz. Previously, I was able to compile VIs with DRAM clip nodes in timed loops running at 100 MHz without any problems.
The compilation fails with this summary:
"Compilation
failed due to resource overmapping"
although it should fit easily.
The error is definitely related to DRAM. This s what Xilinx log says:
"ERRORlace:543
- This design does not fit into the number of slices available in this device
due to the complexity of
   the design and/or constraints.
   Unplaced instances by type:
     IDELAYCTRL    21 (48.8) "
Then it lists these instances (about 20):
   0. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate0
   1. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate1
   2. IDELAYCTRL Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate2
Both DRAM banks are configured with the clip node for 128-bit FIFO version v1.1.0. I also tried using the legacy version v1.0.0 but it didn't make any difference.
It looks like I have some configuration problems I can't identify or there is something wrong with the DRAM clip node in Labview FPGA 2010.
Any ideas on what could be happening here? Any help would be much appreciated.
Regards,
Ivan
Attachments:
flexrio_dram_test.lvproj ‏157 KB
flexrio_dram_test_fpga.vi ‏124 KB

Hello Ivan,
It looks like in your project you are using both the NI 5761 adapter module and DRAM. We have seen a few cases where certain combinations of DRAM, adapter modules, and FlexRIO FPGA targets in LabVIEW FPGA 2010 have caused some resource overmapping errors of the IODelayCtrl components used in the adapter module and DRAM CLIPs. Due to a bug, certain constraints inside of the CLIP cores are misinterpreted by the ISE compiler causing this overmap error when you switch to LabVIEW FPGA 2010.
This was reported to R&D (# 258076) for further investigation and to create a long term fix. In the meantime, for this specific issue please use the following knowledgebase article to apply a patch to your FlexRIO fixed logic files. This patch updates some of the constraints used by the DRAM to ensure that the Xilinx compiler can properly interpret them. There are more details on your issue in the knowledgebase as well.
Knowledgebase 5E4FNCDP: Error, “Compilation Failed Due to Resource Overmapping,” When Using NI FlexR...
If you do run into any other issues regarding IODelayCtrl components, feel free to reply to this forum topic to let me know about them.
Regards,
Browning G
FlexRIO R&D

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Labview FPGA called another software component

Hi
I am trying to compile my FPGA code which has previously compiled. I get this error.
"Labview FPGA called another software component, and that component returned the following error:
Error Code: -52009
NI Platform Services: The requested resource has been marked for deletion and is rejecting new requests."
What is this error code?

Hi,
I've been looking in to this for you today - unfortunately, that seems to be a really rare error code which doesn't come up very often on our systems, so there's no quick fix that I can find.
A couple of options:
1) Have you made any changes to the code recently, in terms of updating it from an earlier version of LabVIEW? If so, it may be worth mass compiling your project up to the latest version in case there are references to software components which no longer exist.
2) It's probably worth a try repairing your LabVIEW, FPGA and RIO drivers installations from disk, as described here: http://digital.ni.com/public.nsf/allkb/FE6B641E86E55AF2862576DE00038001?OpenDocument
This could be due to some kind of missing or corrupted component in, for example, the Xilinx Tools
3) Are you referencing any kind of external software, such as DLLs or third party instruments, in your file?
4) What hardware are you using?
Please let me know how you get on with these queries.
Best wishes,
Chiara A
Applications Engineer with NI UK & Ireland

HELP -FPGA SPARTAN 3E-100 CP132 WORKS WITH LABVIEW FPGA ?

HI EVERYBODY, IM TRYING TO USE MY FPGA BOARD WITH LABVIEW, BUT I DONT KNOW THAT IF ITS COMPATIBLE, I INSTALLED DRIVERS, FPGA MODULE, AND LABVIEW 2012, IM USING WINDOWS 7 32 BITS, AND AFTER I COMPILE ITS SAID :
LabVIEW FPGA called another software component, and that component returned the following error:
Error Code: -310601
NI-COBS: Unable to detect communication cable.
Please verify that the communication cable is plugged securely into your computer and target. Also verify that the appropriate drivers are installed.
THANK YOU .
=)
Solved!
Go to Solution.

Hi dvaldez2.
LabVIEW FPGA does not offer support for any third party hardware, other than the Spartan 3E XUP Starter Kit. Those are probably the drivers you downloaded.
http://digital.ni.com/express.nsf/bycode/spartan3e?opendocument&lang=en&node=seminar_US
However, this driver only supports the Starter Kit board itself (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,790&Prod=S3EBOARD). You can't use the driver with any other FPGA from Xilinx.
Hope this helps.
Aldo H
Ingenieria de Aplicaciones

Labview 2011 FPGA Compile Error

Hi,
I'm new to FPGA. I want to use Labview 2011 SP1 with the Spartan 3E starter kit from Xilinx (Spartan 3E driver available from NI labview website).
I'm trying to work my way through the examples that came with the driver. I've run into the same compiler error with a number of the examples. The error is attached.
Error 7 occurred at Read from Text File in niFpgaCompileWorker_CheckForErrors.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:1
Possible reason(s):
LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.
C:\NIFPGA\compilation\Shift_FPGATarget_Shift_87E8371C\Spartan3EStarter.bld
I've checked the registry to ensure that the path to the compiler is correct.
Any assistance would be welcome.
Regards,
James.
Attachments:
Labview2011_FPGA_CompileError.JPG ‏96 KB

Hi,
I don't have any Xilinx tools installed - other than the ones that installed with the Labview FPGA module.
I have attached the compilation logs and output results from my attempt.
I have renamed the extension on the following files from .lvtxt to .txt
BuildResults.txt
CodeGenerationResults.txt
Regards,
James
Attachments:
BuildResults.txt ‏5 KB
XilinxLog.txt ‏42 KB

LabVIEW FPGA: The compilation failed due to a xilinx error

I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd ignored due to errors
-->
Total memory usage is 204688 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
Compilation Time
Date submitted: 2014/2/26 18:15
Date results were retrieved: 2014/2/26 18:17
Time waiting in queue: 00:06
Time compiling: 02:02
- PlanAhead: 01:16
- Core Generator: 00:00
- Synthesis - Xst: 00:35
Solved!
Go to Solution.

I have got the same error, Have you solved this error?
What you have done?
jasonneu wrote:
I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd ignored due to errors
-->
Total memory usage is 204688 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
Compilation Time
Date submitted: 2014/2/26 18:15
Date results were retrieved: 2014/2/26 18:17
Time waiting in queue: 00:06
Time compiling: 02:02
- PlanAhead: 01:16
- Core Generator: 00:00
- Synthesis - Xst: 00:35
Mahran

Labview FPGA compile stuck at "Place and Routing"

I am using LabVIEW 2010 SP1 32-bit FPGA module. I've built a very large program that was first done back using LabVIEW 8.6, so I have several years experience on LabVIEW FPGA.
When I say it's a large program, I mean that a several times over the last couple years I've tried to add more functionality that has failed to compile do to not enough space on the target or timing restraints. My target has mostly been the PCI/PXI NI-7813R. Due to the nature of our product, a lot has to be done on one FPGA board.
When I do go "over the limit" the compile (after a couple hours) fails and tells me that there's just not enough room on the 7813.
Recently, however, I added some more code, thinking the odds were good that it might push me over the edge. However, the compile never fails. Unfortunately, it never stops either. It gets to the "Placing and routing" portion of the compile and just stays there. When I say stays there, I mean I've run it over night, and when I check it the next morning, the "Elapsed time" is over 10 hours, and still counting up. The device utilization and estimated timing numbers are all under max. And I see no errors in the report so far that I'm used to seeing. Like I said, it just keeps compiling.
I've attached the Xilinx log. It looks much like the log before I added the extra code, except it just stops logging with reporting any useful error.
Anyone have an idea what I could be doing wrong?
Thanks,
Rick
Attachments:
XilinxLog.txt ‏3936 KB

tannerite,
Thanks for your response.
I added code that measures the "on time" of incoming DIO pulses. If the pulses are HIGH for one given amount of time (eg. 60[+/- 5] usecs) it means one thing, if HIGH for a different amount of time (eg. 120[+/- 5] usecs) it means something else. Generally speaking, I just keep a tick count between the rising and falling edge of the pulse, and use the "In Range and Coerce" from the Comparison Functions palette to check where the count lies.
When it compiled successfully, I duplicated the above code for 10 seperate DIOs. Then I realized I needed to monitor 20 DIOs. It was when I added the code for these extra 10 DIOs that I got the "forever" compile. The compile problem occurs everytime I try to compile with the extra 10 DIO code in place. As an experiment, I just added 4 extra DIOs, i.e. code to monitor a total of 14 DIOs. This causes the same compile problem.
And yes, the compile seems to hang in the same place every time it hangs. Like I said, I wouldn't be surprised if I'm just beyond the available resources available. But when I've done this in the past, the compile does finally fail, and I get a useful error message. I've never seen it go "forever".
Thanks ahead of time for any insight you might have.
- Rick

FPGA Compile Error due to error in mapping process

Received the following error while trying to compile a FPGA VI on a PC. (Refer to attachment for details). My PC has a fresh installation of English Windows 2000 with sp4. No other software is installed except LabVIEW 8.2 & FPGA Module 8.2 & NI-RIO.
I have checked this KB and confirmed that regional settings are English. But the error still exists. I tried compiling the same VI on my laptop with Windows 2000 sp4 and it was successful. Can someone help me? Thank you very much!
FPGA Compile Error When Compiling LabVIEW FPGA VI
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
Design Summary
Number of errors : 17
Number of warnings : 8
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
Message Edited by maimai on 01-08-2007 01:00 AM
Attachments:
FPGA Compile Error.txt ‏8 KB

Hello,
The key will of course be to isolate differences between your machines.
I wonder if the following more specific language setting could be the lingering problem. LabVIEW is a non-unicode program, and there is a language setting in Windows (at least XP) specifically for non-unicode programs. Try the following (or it's Win2K equivalent) if you haven't already:
0. Open "Control Panel"
1. Open the "Regional and Language Options"
2. On the Advanced tab, choose English (United States) from the drop-down menu under the top section "Language for non-Unicode Programs"
- This language setting is different from the setting on the "Regional Options" tab.
Any other differences you can isolate would be potentially insightful - if you have the same software versions installed in the same order on both machines, we may be looking for something a bit subtle, such as the suspected language setting.
Best Regards,
JLS
Best,
JLS
Sixclear

Compiling errors under LabVIEW FPGA v1.1

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