Configuring 6533 transfer mode and parameters

I'm a PhD Student at the University of Naples, Italy.
I'm planning to use a PCI-DIO-32HS (PCI6533) board for my application, but unfortunately I haven't got this board at hand yet.
I'm currently designing the software program, and I need to know how I can configure the following characteristics:
- grouping ports;
- transfer direction;
- handshaking protocol;
- ACK/REQ polarity;
- interrupt/DMA;
- startup sequence;
- programmable delay.
Fundametally, I wonder whether all these characteristics can be configured "off-line" via MAX, or rather it is strictly necessary to build a set of VIs to enforce the parameter values in the LabVIEW program.
My aim is to use the PCI-DIO-32HS board for obtaining two inde
pendent groups (one for input and another for output) using unbuffered handshaking.
Could I use the "Dig Word Handshake In(653X)" example VI to build upon it my application, and **at a later time** use MAX for setting all the characteristics listed above? And, if this is not possible for all the above characteristics, which one need to be set explicitely in the LabVIEW program?
I really thank you for your attention.

You won't be able to do this configuration within MAX. You will perform this configuration within the programming environment (LabVIEW in this case).
I would definitely use the shipping example programs within LabVIEW as a reference and a starting point. The example program you mention has two VIs (Digital Group Config VI and Digital Group Read VI) that allow you to configure the options you mention (grouping ports, direction, etc...). I would take a look at the help for the digital VIs used in example programs to see which VI can do what. The Digital Mode Config VI can be used to set the handshaking protocal and the ACK/REQ polarity.
I hope this helps.
Regards,
Todd D.
NI Applications Engineer

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    I am not aware that using the Scan Engine is blocking any access to a transfer FIFO. But please reread this from your quoted KB:
    Secondly, the number of DMA FIFO's that can be used in the FPGA code will be reduced, since the scan engine uses two DMA FIFO's. Most FPGAs have 3 DMA FIFO's, so there will only be one DMA channel left to use in the FPGA code.
    This means, you have only a single DMA FIFO left which is either Target to Host or Host to Target.
    Make sure that you configured the FIFO to be the correct direction for your needs...
    hope this helps,
    Norbert
    CEO: What exactly is stopping us from doing this?
    Expert: Geometry
    Marketing Manager: Just ignore it.

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