Cycle/loop formation in simulation loop

Hello
I am having a problem where output of block 2 is input to block 1 and output of block 1 is input to block 2.
There is a feedback node which allows to specify initial condition but it runs simulation only once. As far as I know while loop and simulation needs to be kept seperate.
Shift register can be another method to upadte it every time. But then also my simulation loop will have while loop inside.
Please see attched snapshot n it will give better idea
T and q are input/output for eacjh other
Thanks in advance. 
Thanks & Regards,
Kunal Raithatha.
CTD - CLAD (I wish I can take off that A, and maybe use it later to replace D :-)
Easy Tip :- "To copy an image to a VI icon, drag the image file and place it on the icon
located in the upper right corner of the front panel or block diagram" ...If you know any
more reply back.
Attachments:
Screen shot 2010-11-30 at 2.41.26 PM.png ‏12 KB

As long as at least one of the outputs is fed indirectly by the inputs, then you will not have an algebraic loop. Otherwise, use the memory block which behaves like a shift register but takes into account the state of the simulation. The memory block is on the Utilities palette for Simulation.
"There is a feedback node which allows to specify initial condition but it runs simulation only once"
Do not use the feedback node; stick with the memory block. I am not sure what you mean about the simulation running only once, but the feedback node will not behave as you expect.
Avoid trying to use while loops in your simulation. Do not try to introduce "states" (like shift registers) that are external to the simulation. Simulations do things like take minor steps along the way and sometimes even reject steps and start over, and your externally introduced state will be incorrect if this happens. For example, let's say you create a VI with a while loop that increments a value whenever the VI is executed. If the simulation decides to reject a step and take a smaller one, your increment will have already incremented and will not know to roll back its state.
Hope that helps.
Damon

Similar Messages

  • Cycle / Loop Drops Notes when reaching end of loop

    Hi there!
    Very annoying situation seems that when I first create a song, put a cycle/loop on four bars (cycle range) it goes round and round fine, no drop outs.
    I picked up a song I did three days ago, changed nothing and it seems when it gets to end of 4th bar and goes back to first bar I get drops/pauses sending midi notes to my synth. As I have jam pack layeers in the song, if I mute the midi, I realise that the jam pack layers sound as they should do - it's just the midi that skips/drops.
    If I take off the cycle range and loop the layers then there are no drops. Any ideas would be much ly appreciate, this is rather pain!!
    Many thanks,
    Philippe

    I have had this happen sometimes. It depends on what "voice" your MIDI notes are playing. Some of them have things like reverb and echo on them that require the playhead to move beyond the region to output the sound. Sometimes you will only get the sound cut off too quickly.
    If you move the cycle region beyond the end of the segment you should be able to hear the notes.

  • Stuck in power cycle loop

    So last night my Apple TV was going through its normal process when it is updating new software. Some where along the lines however the update stopped and now it is stuck in a power loop. I have read from others that they can get to the main menu and all that but all I am able to get is the starting picture of an apple and it sits on that for about 15-25 seconds and then it turns off again. I have tried to power cycle by unplugging it, pressing and holding the menu and play button, I left it unplugged all night and tried again tonight, so far the problem is still going on. I have more recently plugged it in to the internet souce directly (ethernet cable) and have been letting power loop hoping that it was just going to finish up... thats not the case. Any help or suggestions would be super. Thanks
    - J

    Yeah I did unplug the HDMI, power cable, and ethernet internet cable... I then used a Micro USB caple to plug it into my computer and it didn't work. I know some of the USB ports are powered differently but I did try both of USB ports and still it didn't work. I went as far as to make sure that I didn't have any other USB device plugged into my computer making sure that the power wasn't being diverted. Unfortunatly this still resulted in the same problem. I could see the white light on my Apple TV and it was blinking like it has been doing since the problem first appeared... Thanks again for taking time to ensure accuracy but I belive this Apple TV will need to be sent in and I will have to purchase a new one.
    - J

  • Creating new tracks when recording in Cycle (loop) mode

    I'm having an issue when recording in cycle mode.. I'm able to record (in seperate tracks) in cycle mode. however I can only play the first take (first track) I recorded, however all the subsequent tracks that were recorded do not play. Even when I try 'soloing' them they still don't play. You can see in the arrange window that audio data was recorded on those tracks however they have a "faded" effect to them. They're also not muted. Am I missing a setting?

    The issue you describe when recording in cycle mode was a huge frustration for me until I discovered that I was not aware of a simple principle that made all of the difference... I am wondering if the following explanation may be part of the problem that you are experiencing.
    The principle is that muting a region, muting a track, and muting an audio channel are three distinct and separate functions. Until I got my head around that principle, I continued experiencing the same frustration that you are having with recording in cycle mode.
    Recording in cycle mode results in muting the regions below the last take at the top. When trying to unmute the "tracks" below the top region to listen to the other takes, hitting the mute button results in ALL of the "tracks" either being muted or unmuted, yet the separate regions below are still muted!
    The key is to unmute the REGION that you want to listen to (and not the track or the channel). The way to do this is to hit the escape key to bring up a local tool box menu wherever your cursor is... then click on the mute tool which changes the cursor into a mute tool, then click on whatever regions you want to unmute...
    Hopefully the above will help.
    Power Mac G5   Mac OS X (10.4.8)  

  • Animated Gif- want to loop some frames, then others

    I'm creating some web banners, and I need the file size to stay low, but would like to have a 3 or 4 frame cycle loop for a while, then go to a frame that holds for several seconds, then back to the loop, and then another frame that holds. So really all there is is 6 total frames, but in order to make it play out how I want,  I have to set like 30 frames in the animation window, each one of the 6 total, and then the file size is enormous compared to  what really should be possible, its basically treating it as though I have 30 distinct frames. Isn't there a way to make an extended animation using a only handful of frames, and have the file size not balloon up?
    Another thing I'm trying to do, to cut down in file size, is have the animated portion be real lossy, since its quick and detail is not important there, but have the frames that hold for a while be higher quality. But there doesn't seem to be a way to do that... why not?
    Thanks for any advice,
    Andrew

    But there doesn't seem to be a way to do that... why not?
    Well, you are using GIF, aren't you? That pretty much covers all the options. These are limitations in the file format, plain and simple. There is no such thing as a per-frame local palette, all 256 colors are distributed across all frames. So if the content requires a certain amount of colors, the algorithm merely tries to balance itself out. Likewise, the frame behavior is dictated by the file format specs, so there is realyl nothing you can do. As Zeno said, you'd have much better luck doing this in Flash using pre-processed PNGs and a few simple timeline commands with goto().
    Mylenium

  • Use the LabView time delay in a while loop instead of using the instrument inherent time loop.

    I have a zes lmg500 that I use. It has the option of continues measuring data, with a user control cycle loop (still using a while loop but the delay is coming from the instrument). The problem is that the loop time is not constant. Can I use a very short time (100ms) as the instrument cycle time but use a longer time delay in the while loop that collect the data?
    I know many instrument offer the same abilities, so the question is relevant to all of them.
    Thanks for any help
    Solved!
    Go to Solution.

    Does that measurement VI have built-in wait functionality and a timeout?
    If not, then you are simply polling the VI at 1 kHz, but I suspect that this is not the case or your Waveform Chart probably wouldn't look as you expect (getting 0's put in everytime measurement data is not available).
    I expect that if you have the instrument set up to send data at a fixed time interval (i.e. 100 ms), all the data that it is sending you will end up residing in your serial buffer (or the instrument driver will have taken it out and put it in another internal buffer), so if you come back to read it 1 sec later, then you will have 10 data points to go through.  Whether you can read them all at once with the read VI or have to call it a whole bunch of times until empty I can't say.
    What is your objective?

  • Looping playback doesn't work

    The WaveBurner manual says you can loop playback in Waveburner by dragging in the time ruler to create a cycle area (page 32 of the PDF manual). This used to work for me but no longer does. Dragging in the time ruler does zilch.
    Anyone else having this problem, or know a solution. Looping playback was very helpful for working with plug-in settings. I'm not sure when this functionality was lost. Possibly with the installation of 1.6.1?

    Hi audiophile31,
    Thanks for the solution! It's interesting to note that this only works in the TOP time ruler. The manual indicates it should work in either ruler (as I recall). And, you're right, the cursor does have to be close to the playhead.
    Hopefully Apple will update the manual...or the program to be more intuitive. NOTE TO APPLE: It would be nice if there were an option (or default) to start the loop from the start position each time you hit the play button (rather than from where you left off in the loop). This was a feature requested in another string that I thought might be accommodated using the cycle loop (except I couldn't get it to work, hence my original posting). It would also be great to be able to set up two cycle areas and alternate between them by hitting option-play or some such command. I often import multiple mixes of a song and adjust plug-ins to compare the differences. Having two cycle areas I could alternate between would be really helpful in A/Bing the changes.

  • When using outlook and trying to retrieve my emails, my system is in this continual cycle of Connecting, Checking for mail, updated -

    When using outlook on my iphone and trying to retreive my emails, my system is in this cycle of connecting, checking for email, updated - This cycle loops after 3 seconds and begins again - I'm still receiveing my mail but it is draining my battery at a rate of 20% per 15 minutes

    Outlook is a mail client for PC's and Macs. There is no such thing as "Outlook" for iOS.

  • OFF-Cycle payroll error Resigned employee

    Hi Experts,
    I have a very typical problem here faced by the employee ;-
    The scenario is this
    Employee resigned during the last year , his payroll area changed to inactive
    The last results available in the cluster for the employee belongs to period somewhere in june 2008 month of resignation
    In the current financial year , company  wants to pay bonus to the employee.
    So the employee was again put in to active payroll area with effective date 01..09.2009  for processing the payroll usiing 0267
    In Infotype 0003 , the run up to date has been updated has 30.09.2009
    in pa03 , the payroll control record has the status has the exit in the Aug-2009 , not yet released in Sep-09
    so ideally , when wwe are processing the off-cycle after the above mentioned steps, it should process the payroll in off-cycle.
    In the simulation it is processing, but coming with a message that                                                                               
    " Payment date of payroll 04.09.2009 later than period end of next payroll  31.08.2009"
    But when we try to finalise the cases it is throwing up the error mentioning the same.
    We are not able to finalise the Off-Cycle payroll for such cases.
    Anyone please can help me in this ?
    Thanks & Regards
    Srijit R Menon

    Hi Sadhu / Sikandar,
    Thanks  for the reply,
    I checked with CYFRM , it is given as 1 only,
    again , for the terminated employees the final run was made in the month they were terminated., in june-08
    And while doing offcycle run does the payroll driver checks the past period resuts, i m not sure
    even if it checks , the offcycle is allowing me in quality system with the same data ,  data in quality & Production is equal, as we have updated our quality system recently by copying the production.
    In Quality its working , and not giving any errors and issues, the pa03 is also in the exit mode of aug-09 , the payment date is given as 04.09.2009 in 0267 . its allowiing me to simullate and final it
    Kindly help

  • Trasnfer function error usgin ULx library for running a DC motor

    HI,
    I am trying to run a DC motor using Labview's control kit. I want to add a transfer function to the system but once in the loop it gives me an error. The function has an added zero to see changes in the system. It is given by :
    H(s)= (1/5s +1) / s
    There is no error if the added zero is removed. I am aware that the degree of numerator cannot be greater than that of denominator but this has same degree. It works in Matlab . Labview for some reason does not accept it. Any help would be appreciated. Please do let me know if I am going wrong somewhere.
    I am attaching the file and pictures of the block diagram and the error incase you cannot run the file.
    Thank You,
    rps
    Attachments:
    lab5_motor close.vi ‏48 KB
    error.png ‏97 KB
    blockdiagram.png ‏42 KB

    Hi rps,
    Are you still having trouble? Adding the zero changes the feedthrough of the Transfer Function from Indirect to Direct. Are you using the error wiring and the Merge Errors to control the execution of your program? The error handling of your program creates a cycle that requires the Transfer Function to have indirect feedthrough. This is explained in the “Wire: is a member of a cycle” Errors with the Simulation Module knowledge base article.
    Changing the error handling to avoid the cycle or using a Transfer Function with Indirect Feedthrough should resolve this issue.
    I hope that information is helpful!
    Matt
    Product Owner - NI Community
    National Instruments

  • HP system restore and factory reset not completing

    Hello.
    1:  Person tried a system restore to fix a user profile problem but once booted the OS changed the  user profile to "temporary" every time, checked the original profile but only the avatar was left , all other personal info was gone.
          Working through "profiles list" in the registry and setting back to the original user profile from temp profile didn't work and went back to temporary.
          Complete erasure  reset of all user profiles includig in the registry didn't work either. Went back to temporary profile.
          It was no use to save any files while the OS was in this stat as every reboot would remove the files including in the temp profile.
     2:  Tried all basic boot/DOS HP recovery for installed windows OS with no success, all system restore backups back several months failed.
    3:  Tried a factory reset twice and while it did restore for the most part with the automated drivers installed the HP recovery  returns an error that factory reset did not or could not complete itself.  This was attempted twice.
          While one could shut down the HP error screen in windows 8 and continue the failed reset booting error was still logged and it defaults to the HP receovery which ends up looping over and over again.
           while still in windows once the HP error is closed one can goto the usual user name and password so  that was done  twice and with the simplest password.
           Problems compounded when the OS rebooted and asked for user name and password, which returned "not valid" over and over again.   One time i entered the user "administrator" with the password "admin" and it worked, it started loading but then returned invalid username or password.  Point being that  that was not the actual user name and passowrd that was chosen and confirmed.
           This part of the problem is the same as the first problem
    3A:  I wiped the main and system partitions and reformatted them  and ran then HP factory reset once again, it restored faster than the first attempt, however it dropped to the same username/password error and i can't even get into safe mode any longer.
    Again the system boot sequence registeres the restore as incomplete but i can boot select OS which is how i am able to get into windows to test the User/pass.
    4:  I beleive that there is hardware malfunction with the hard drive controler in this system as i noticed that UEFI is intermitant no matter what settings you set in the BIOS/CMOS.  When UEFI boot CD/DVD does appear in the boot selection it can't detect the cd/dvd drive or a USB drive "invalid device".
         Many of the boot options even when set in the bios will not always appear in the boot selector on every power up that includes legacy.
          While i can boot from CD/DVD with the legacy boot selection. I can't install windows 8 or 7 becasue the HD is A GPT and without UEFI i don't get advanced options in the windows OS install partition setup.  Windows 7 or 8 won't install becasue the HD partition is a GPT format even after i wipe those paritions and make new ones with basic NTFS.
          I could LLF the HD and hope that i could install windows 7 but the UEFI being intermitent would probably return the same resutls as the HP factory reset.   Similar problem with older computers when enabling AHCI in windows.
         If i LLF the HD i loose the HP recovery completely.
    Any suggestions?
    Thanks.

    Hello.   The laptop is an HP Pavilion dv6 notebook PC
    I have since LLF'd the HD and installed windows 8.1.  It's still touchy but it's working for the time being.
    A: The laptop's owner did a standard windows system restore
    B: I did two windows system restores  as well as backups.
    C:  Yes i usd the F11 at boot  recovery system to run windows system restores, cleanings, and finally the factory reset. Which is obvious as i stated above that if wiped both main windows partitions and it helped the factory restore speed so only restoring an image will replace the OS on the now empty partition.
    D:  No i didn't keep the failed restore logs as they were randomly scrambled with all the recover cycle loops (both times).
     Also i should mention that the factory restore once it failed the completion i got "insufficient sapce"  error as well  which i am guessing that it's trying to write the log file.
    If memory serves there was only 40mb left on the recovery partition.  Yes MB not GB.

  • Running data at different rates within a SCTL for resource sharing

    I have a design that contains several single cycle timed loops (SCTL):
    (40MHz SCTL) -> (20MHz SCTL) -> (40MHz SCTL) -> (10MHz SCTL)
    The first 2 SCTLs are decimation filters so that the data coming out of the 20MHz SCTL is
    at a 10MHz sampling rate.  The 2ns 40MHz SCTL is filter that is 4X resource
    shared so that I can use the available dsp48E slices.  I'm using target-scoped FIFOs to
    pass the data between the loops.  In simulation, I have the timeout set to -1 so that it reads
    from the FIFO whenever there is data available.
    When I run the simulation, I expect/want to see my control counter running 4 times faster
    than my incoming data.  I thought that since the data was written into the target-scoped
    FIFO at a 10MHz rate and the control counter is in the 40MHz SCTL, I would see the
    behavior I wanted:
        X     a     X     b      X      c     X     d     X  <- data from FIFO
        X0X1X2X3X0X1X2X3X0X1X2X3X0X1X2X3X  <- modulo-3 counter
    Instead I see the data and counter essentially running at the same rate:
        X1X2X3X4X5X6X7X8X9XaXbXcXdXeXf X0X    <-data from FIFO
        X0X1X2X3X0X1X2X3X0X1X2X3X0X1X2X3X    <-modulo-3 counter
    Also the iteration counter for the SCTL runs at the same rate which seems to indicate that the
    loop only executes when data is pulled from the FIFO.   I was expecting the iteration counter
    to be at 3 before the second sample was read from the FIFO and at 7 before the third sample
    was read from the FIFO. I'm guessing that the simulator is event driven.
    I have a couple of questions:
    1. How can I  get the behavior I'm looking for?
    2. If not, can I expect the behavior I want if I run this on the hardware?

    update:
    NI support suggested using the FIFO timeout signal to determine when the data is valid
    coming out of the FIFO.  I was using a -1 on the FIFO read to read only when a sample
    was available.  NI support said to use a 0 and then gate the data based on the timeout
    signal.  The behavior of the design changed, but still did not give me the timing I was
    expecting.  Instead of seeing my counter update on every new sample, I see the SCTL
    "free running"  It's difficult to determine if the counter is behaving properly, but I do see it
    running faster.  The problem is that the SCTL seems to be running much faster was well.
    Using the -1 on the FIFO read I would see > 262K samples written out for every 1000 in.
    Using the 0 on the FIFO read and gating the data based on the timeout signal, I see
    >60K samples for every 1000 read in. I'm expecting 250 samples out for every 1000 in.
    Can someone tell me what controls the behavior (in terms of execution0 of the SCTL?  It
    seems like it is event driven, but I need the design to be clock or cycle driven for both
    simulation and execution of the hardware.
    Regards,

  • Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

    Dear Friends, 
    Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers! 
    1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
    I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money? 
    I’m looking for a comparison can show the following points:
    ·         The Code size and speed optimization.
    ·         Developing time.
    ·         Compiling time.
    ·         Verifying time.
    ·         Ability to developing in future.
    ·         …etc.. 2-     
    I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
    The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
    Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
    3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
    4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?Nav​Path=2,400,599&Prod=XUPV5 
    Thnaks & regards,Walid
    Solved!
    Go to Solution.

    Thanks for your questions and I hope I can answer them appropriately
    1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
    Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
    Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism.  I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
    Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
    Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
    Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
    2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
    3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
    4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
     I hope this has anwered some of the questions you have.
    Regards 
    Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
    Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

  • How can I found out the timing (ticks) of Functions for the FPGA (7833R PCI)?

    Hallo,
    I have problems to measure times. My measured time is not constant it jitters too much. I need a maximum jitter of 5µs and I had heard that I can solve this Problem if I programm code that is faster than 5µs on my FPGA, so I must know how long does the fuctions need by running the code!
    Who can I find this Information?
    Martin

    Hello Martin,
    I don't know how long the functions need to run the code.
    But there are a few things you can do to speed up your code.
    One thing is to use a single cycle loop for your code, which removes some overhead.
    A second thing is to do calculations in parallel. Search for 'pipelining'  .
    Hope this helps.
    Uli

  • Discoveryd Basic Sockets Couldn't set IP_BOUND_IF on socket fd[72] scopeID[4] errno[22] result[-1]

    message loop filling system log.
    Text: discoveryd Basic Sockets Couldn't set IP_BOUND_IF on socket fd[72] scopeID[4] errno[22] result[-1]
    Value of fd[] does cycle
    Loop prevents access to internet
    Tried work-around from http://apple.stackexchange.com/questions/153080/computer-name-keeps-changing-osx -10-10-14a389
    Basely has an affect.
    Power-off of router stops the loop.
    Powered-off for 5 (five) minutes and can access internet
    Macbook Air (MBA) and iMac both experience the loop

    Please read this whole message before doing anything.
    This procedure is a diagnostic test. It’s unlikely to solve your problem. Don’t be disappointed when you find that nothing has changed after you complete it.
    The purpose of the test is to determine whether the problem is caused by third-party software that loads automatically at startup or login, by a peripheral device, by a font conflict, or by corruption of the file system or of certain system caches.
    Disconnect all wired peripherals except those needed for the test, and remove all aftermarket expansion cards, if applicable. Start up in safe mode and log in to the account with the problem. You must hold down the shift key twice: once when you turn on the computer, and again when you log in.
    Note: If FileVault is enabled in OS X 10.9 or earlier, or if a firmware password is set, or if the startup volume is a software RAID, you can’t do this. Ask for further instructions.
    Safe mode is much slower to start up and run than normal, with limited graphics performance, and some things won’t work at all, including sound output and Wi-Fi on certain models. The next normal startup may also be somewhat slow.
    The login screen appears even if you usually login automatically. You must know your login password in order to log in. If you’ve forgotten the password, you will need to reset it before you begin.
    Test while in safe mode. Same problem?
    After testing, restart as usual (not in safe mode) and verify that you still have the problem. Post the results of the test.

Maybe you are looking for