DMA FIFO

Hi,
I am writing 400 elements to a DMA FIFO of the NI7831 FPGA Target, the DMA FIFO depth was defined in the FPGA FIFO Properties to 127 elements.
The FPGA Target is running in emulation mode.
No DMA read routine at Host side is running.
So, I was waiting for the FIFO Full Flag but it never rise.
Is there a failure in the write routine or do I something wrong ?
Peter

The full flag will never be set in emulation mode. Data is not actually transferred into the DMA FIFO until the DMA engine starts. The DMA engine starts using the Host VI. So without a host interface VI to start the DMA engine, data is never going into the DMA FIFO.
Regards,
Joseph D.
National Instruments

Similar Messages

How can i send more than one signal to DMA FIFO?

Hello,
I'm trying to send more than one signal to DMA FIFO, but i don't know how to do. When i send one signal i don't have problems. I try to use one block DMA FIFO for one signal. For example if i have 3 signal i use · DMA FIFO but whe i want to wath them in a waveform chart the signals have a delay.
How can I do to send more than one signal to DMA FIFO? and if that's no posible, How i can do for syncronizate the 3 signals?
The data type of the signal is FXP <16,10>
Regards.
Pablo
Solved!
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Attachments:
Block Diagram.jpg ‏81 KB
Block Diagram.jpg ‏81 KB

Not quite. You need to use the Integer To Fixed Point Cast to change from the integers to your FXP numbers. You can then build them into a cluster to write to the Waveform Chart.
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Attachments:
Combine and Decode FXP.png ‏14 KB

Fpga DMA FIFO compilation error

Hello,
I have a cRIO 9074 with FPGA. I am trying a simple piece of code to learn how to aquire data that is generated on the FPGA at a rate of 10 KHz and transfer it to the Host VI for processing it later offline. However, I encounter this compilation error when compiling this basic FPGA VI containing a FIFO
write node (picture of the VI attached below). In the Compilation Report, it says that there were 256 Block RAMs used (the
total number is 40), therefore an error was produced. The exact compilation error
notification from the Xilinx report is reproduced below:
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow -timing toplevel_gen.ngd
toplevel_gen.pcf
Using target part "3s2000fg456-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
ERRORack:2310 - Too many comps of type "RAMB16" found to fit
this device.
ERROR:Map:115 - The design is too large to fit the device. Please check the Design Summary section to
see which resource requirement for your design exceeds the resources available
in the device. Note that the number of slices reported may not be reflected
accurately as their packing might not have been completed.
NOTE: An NCD file will still be
generated to allow you to examine the mapped design. This file is intended for evaluation use only,
and will not process successfully through PAR.
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
Number of errors : 2
Number of warnings : 125
ERROR:Xflow - Program map returned error code 2. Aborting flow
execution...
Bitstream Not Created
Timing Analysis Passed
What does this mean? How can I fix this error?
Thank you,
Bogdan
Solved!
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Attachments:
FPGA.png ‏16 KB

Sorry, I forgot to mention that...LAbVIEW 2009. And yes, this is the only loop on the FPGA.vi. I just made up this code to understand how exactly I would save some data on the host for subsequent processing, but I didn't get to that point because the VI on the FPGA does not compile successfully. Do you know of any example of the most basic code for DMA FIFOs between the FPGA and Host Computer? This should be pretty straight forward, but for some reason it's not.
Thanks,
Bogdan

How can i decide the depth of all3 DMA fifo's are used as target to host at RT contoller side(host)?

Hello,
I am using all DMA fifos,I want to acquire data from 3 AI modules upto 50 khz frequency.Sampling rate can be varied according to application.
please suggest me how should i allocate memory of my RT controller for those DMA fifos?I am also facing one problem, I am using 3 time deterministic loop with different different priorities,each time loop has one fifo where data is reading with polling method(first fifo.read=0 then againg fifo.read=remaining elements).and each time loop has been interact to host vi with global varibales.those global variables data update from normal time loop.can anybody suggest that this procedure is right or not.if my problem is not much clear i will again explaing my query with snapshot of my application.
Pratima
*****************Certified LabView Associate Developer****************************

You wouldnt need to allocate memory separately on your RT Controller for the FIFOs. You need to create a FIFO under your FPGA target and use the FPGA interface VIs in your RT VI to access the DMA FIFO. You would need to use the FPGA interface invoke method VI to access your DMA FIFO.
As for the other questions, I would recommend you to create a separate post the RT section of LabVIEW so that you can get a faster response to your questions.
I hope this helps!
Mehak D.

Passing data from RT host to FPGA through DMA FIFO

Hello,
I am trying to write some data from an RT host to FPGA target using DMA FIFO then process this data and then read them back from the FPGA target to the RT host through another DMA FIFO. I am working on NI PXIe chassis 1062Q, with NI PXIe-8130 embedded RT controller and NI PXIe-7965R FPGA target.
The problem I am facing is that I want to send three different arrays, two of the same size and the third one with different size, and I need the smaller one to be sent to the FPGA first. I tried using flat sequece with two frames in the FPGA VI. In the first frame I read and write the first array in a while loop which is finite (i.e., finite number of iterations). The second frame contains the process of reading and writing the second two arrays (of the same size) in a while loop that can be finite or infinite (according to a control). The problem is that this didn't work. The 2 arrays are displayed on the front panel of the RT host VI and are working fine, however, the array that should have been read in the first sequence doesn't show up on the front panel of the RT host VI. This doesn't make sense because if it is not passed from the host to the fpga and vice versa then the second frame shouldn't have been executed. Note that I am wiring (-1) to the timeout to block the while loop iterations till the passing of each element is complete. Thus the first while loop has 3 iterations only. Could someone help me undersdtand why this happens and how to solve this problem?
I am attaching a picture of both the host and the fpga vi.
Thank you.
Solved!
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Attachments:
RT host vi.png ‏102 KB
FPGA vi.png ‏28 KB

No need to initalize the arrays with values that you will immediately overwrite. Here's what I believe to be equivalent code:
The array outputs should be wired directly to the FPGA FIFO writes. Do not use local variables when you can wire directly.
If you know that you want to transfer the Temp Data Array first, why not make your code do that? Eliminate the sequence structure, and put the functions in the order in which you want them to execute. Use the FPGA reference and error wires to enforce that order. You might consider writing the Temp Data Array, reading it back, then writing the Real and Imag A arrays, to see if that gets you the results you expect. Run the code in simulation (in the project, right-click on the FPGA target and execute on the host with simulated IO) so that you can use execution highlighting and probes to see what is happening. Wire the error wires through and see if you get an error anywhere. Make sure you're not missing something simple like looking at the wrong starting array index.

DMA FIFO number of elements to read mismatch in FPGA and RT

Hi all
I am using myRIO , LV14 to run my application.
Application: I have to continuously acquire data via FPGA and process in RT host once every 2000 samples are collected. I use DMA FIFO (size 8191) to acquire data, use timeout property at the FPGA to eliminate buffer overflow. I had followed cRIOdevguide to implement this part. A snippet of what I have implemented is attached. Whole code runs in SCTL at 50MHz.
Issue: Twice or thrice I encountered with this strange behaviour, that the FPGA FIFO is giving continous timeout and the RT is unable to read the FIFO. The number of elements to write propery in FPGA VI gives 0 showing that FIFO is full and no more can be written, but at the RT, elements remaining is giving 0, hence it is reading 0 (no) elements.
Workaround: I put a case where I will write to FIFO (as per the code) and if the number of elements to write is nonzero. It seems to work fine, as of now.
What confuses me is that my FPGA VI says that FIFO is full (FIFO number of elements to write = 0) and gives a timeout error, but RT VI says that number of elements remaining in FIFO is 0 and hence no data is read. Any idea why it is so? My FPGA and RT VIs continues to run, but with no data being acquired or read.
I saw this behaviour within minutes after running the code. Any idea as to why it is happening? I am trying to reproduce the behaviour and will update if i again encounter with it. Sorry, I cannot post my code here, but i guess the code snippets explain it to some extend.
Thanks
Arya
Edit: Even with the mentioned workaround, the problem persists, now that the FPGA does not write to FIFO at all. And the RT VI is not able to read any elements as it sees 0 elements in the FIFO. The FIFO continues to be in timeout state. So i guess the problem is with the RT side.
Solved!
Go to Solution.
Attachments:
cRIOdevguide_FIFOreadwrite.PNG ‏107 KB
FPGA_FIFO_write.PNG ‏41 KB
RT_FIFO_read.PNG ‏39 KB

Hi Nathan
Yes, I could have replaced it with an OR. Regarding my application, I want to acquire data in chunks of 2000 samples. If at all I receive a timeout error, I want to discard that chunk of 2k samples and start all over again. So my logic was like this, I acquire the data, if there is a timeout, the reset is triggered, and the system waits to comeback from reset, and it starts acquiring again. Btw, I tried removing the multiple FIFO reads in RT, but the error is still the same.
I have a small doubt as well, if I do not want to obtain stale data at alI, I would just check if timeout occurs, empty my FIFO and start acquiring data again (no reset button), isnt it? This was my original logic, but I saw that after a while, it stopped acquiring data and timeout led was on. I was thinking that FPGA and RT was simultaneously trying to acquire FIFO which might cause timeout. Somehow, I now feel that, as you have pointed out, my code is overly complicated. I will modify it and update the results. Thank you!
Arya

Number of elements in target to host DMA FIFO

Hi everyone,
I'd like to transfer a set of datapoints from a FPGA to a RT-host controller using a DMA fifo. If I use the "Get Number of Elements to Write" function on the FPGA target, do I get the total number of elements in both buffers, or just the one on the FPGA-target?
(see http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/)
Solved!
Go to Solution.

What type of data do you want to transfer over the FIFO? As in how many bits does each sample contain.
The reason I ask is because you can take a bit packing approach.
Lets take for example you want to take two samples of a measerment both samples are 32 bit and then send the data as a set to the processor.
If you just dump the data into a single FIFO you may lose track as to what was the rising edge, or falling edge data, or if the two samples you got from the FIFO are even from the same dataset.
To fix this use bit packing technique.
On the FPGA merge your two 32 bit data sets into one 64bit dataset.
Set your FIFO to 64 bits.
On the processor side of things all you need to do is read one 64bit dataset from the FIFO.
Use the split data to break the 64bit into two 32bit data fields.
Now you have your two data samples, and you can be garentee that it is from the same dataset.
If the sum of the data bits exceed 64 bits (the limit of the FPGA FIFO) then you will need to migrate to a more complex bit packing data schema where the data is split up among multiple 64bit datafields, with a defined bitfield header and identifier. For example the first 5 bits of the 64bit data identifies that this data block is 1 out of X data blocks, that when combinded together and reasembeled per the schema will represent your data..
I hope this helps.

Data transfer from RT to FPGA using DMA FIFO

Hello all,
My question is "How do you stream data from RT target to FPGA target using DMA FIFOs?"
I would like to control some indicators (or controls) in FPGA vi using controls in the RT vi using DMA FIFO.
I have used four controls in my RT vi, but I get only one indicator out on my FPGA vi. (I would actually like to use some controls on the FPGA target using controls on the RT target)
Is this possible?
Can anyone help me with this?
I have attached my vi s.
Attachments:
fpgatest.vi ‏28 KB
rt_test.vi ‏73 KB

Based purely on your example, I see two options:
1. Do as RavensFan suggests and use Boolean Array To Number to send a single number down to the FPGA. Your FPGA can break up the number easily enough to update the indicators.
2. Just write dirctly to the indicators. I do not see a need for the DMA. Again, based purely on your example.
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Query related Internal buffer storage in PXi 7965R DMA FIFO ?

Hello,
I am establishing a communcation from HOST to FPGA by using DMA-FIFO. Maximum size for this FIFO is 1024. Now from the host side, I am writing a data of 1-D array (Unsinged 64bit integer) into the fifo, and from FPGA side, this data is being read from the fifo. Now as i start the simluation, the default value of "Empty elements remaining" shows "10,000". further as the elements inside the fifo starts getting to read (at FPGA side), the "Number of elements to read" increases and when it reaches the value of 1024, then the "empty elements remaining" starts decreasing. The behaviour is described in the image (atteached).
while observing this behaviour of the FIFO, i discovered that this DMA FIFO, (having max. storage elements of 1024) also has an (additional) internal storage space of 10,000 elements. I might call it as internal buffer of this FIFO. now my question here is that, where are these (10,000 elements) values stored ?. as it is from HOST side, so is it the CPU storage ? or what ?
Thanks
Anum Sheraz

ok so I got my answer, its actually the default depth of the DMA FIFO.
Maximum size of this FIFO is set to be 1023, which is coerced to a value of 1029. I did a mistake in the picture (posted in last msg), Here is the correct one;
I've corrected the some of the figures. by noticing its behaviour, when the number of elements to read reaches 1027, then the remaining elementes starts decreasing from value of 10,000. and it reaches to max value of 11027 when remaining elements=0. I am confused with this figure "1027" !!! . why is this 1027 ?
as I have assigned maximum size of this FIFO to be 1023, which is coerced to a value of 1029, so Shouldn't it be 1029 ?.

Reading DMA FIFO using Invoke method node

Hi
I am trying to read a DMA FIFO using invoke method node to read the data in the FIFO on RT.
It works fine but the problem is that it consumes a lot of CPU if the timeout is increased. Can
anyone tell why this is happening and if this is the desired behaviour then what other methods i can
use to avert this.
Please help at the earliest
Regards
Amit

Hi
Can anybody help me as it is urgent ,
What i further found out is that is that it is eating up a lot of meory when continuosly polled up in a looop....
Regards
Amit Ahuja

How to decide the maximum number of elements for DMA FIFO in R series FPGA

Greetings!
I'm working on a project with NI R series PCIe-7842R FPGA board. To achieve fast data transfer I'm using target-to-host DMA FIFO. And to minimize the overhead, I'd like to make the FIFO size as large as possible. According to the manual, 7842R has 1728 kb (216KB) embedded block RAM, i.e., 108,000 I16 type FIFO elements available in theory (1728,000/16). However the FPGA had compilation error when I requested such amount of elements. I checked the manual and searched online but couldn't find the reason. Can anyone please explain? And in general, what's the max FIFO size given the size of the block RAM?
Thanks!

Hey iron_curtain,
You are correct that moving larger blocks of data can lead to more efficient utilization of the bus, but that's almost certainly not the most important factor here. Assuming of course that the FIFO on the FPGA is big enough to avoid overflows, I'd expect the dominant factor to be the size of read performed on the host. In general, larger reads on the host lead to improved throughput, up to the speed of the bus. This is because FIFO.Read is a relatively expensive software operation, so it's advantageous to make fewer calls to get the same amount of data.
Note that the larger your call to FIFO.Read the larger the host buffer needs to be. Depending on your application, it might need to be several times larger than the read size. You can set the buffer size with the FIFO.Configure node.
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/ explains the various buffers involved. It's important to note that the DMA Engine moves data asynchronously from the read/write nodes on the host and fpga.
Let me know if you have any questions about any of this.
Sebastian

Regarding DMA fifo.

My goal is to transfer data to target at its rate. I have the data(array) on the host VI and wants to transfer this data onto the target using a DMA FIFO.
To perform this, i am using two DMA FIFO one at channel 0 which is a host-to- target scoped and the other at channel 1 which is target-to-host scoped.
Depending on the type of the FIFO, i am peforming read and write on those. But i cant find the data on the second FIFO reading at host side.
Can anyone help me in synchronizing the host and the target?

OK give me all information on your project.
Version of LabView.
Details of each target.
Rate of transfert
and if possible an example of your code.
Thanks
Benoit
Benoit Séguin
Software Designer

Too many backlog in DMA FIFO

Hi I am using DMA FIFO for data aquisition. When I only have the data showing on the front panel, the data value is reasonable and the backlog value is around 3. But when I have the write to measurement file block in the block diagram, the back log value will rise to several thousands. How should I make the change to the program to reduce the backlog.
Attachments:
fpgaAcquire.vi ‏108 KB
fpgaAcquire(host).vi ‏187 KB
DMA_FIFO.lvproj ‏193 KB

Buddy Haun wrote:
I looked at your code and you don't have the code you are using to write to disk on this block diagram. I would make sure that your loop time on the fpgaAcquire.vi is set to microseconds instead of ticks which it is currently set to. I would try the TDM Streaming vi's with the Open File and Close file outside the loop so that you are not opening and closing the file inside the loop. There are examples of TDM Streaming in example finder. Lastly if the TDM Streaming cannot be used due to file format restrictions or if it is still not fast enough you may need to create a second loop and use queue vi's to transfer the data. This will allow you to read multiple points from the queue using the flush queue function writing multiple points to the file at once. You will still probably need to open and close the file outside of the second loop. Look at some the Write Datalog File Example.vi to see how to do this.
I did some experiment on the FPGA period. When I set it to be below 400 usec, the data looks almost the same. But when I set it to be above 500 usec. The period of the signal displayed on the screen seems to be multiplied by some constant, and the constant is not proportional to the FPGA period. I will agree with you on using TDMS streaming outside the loop and I will try it.

I32 signed in U32 DMA FIFO

Dear,
In the project, I used a DMA FIFO from the FPGA VI to the Host VI.
I would like keep the data signe (I32), when I recieved the data on the Host.
Can I put the signe on the fist bit? 1bit signe+31 bits unsigned value?
Otherwise how I can do?
Regards
Massif

Hi,
Change the representation to fixed-point and fill in the Fixed-Point Configuration according to the properties of the fixed point data type on the FPGA.
Once the fixed point data is converted, you can use the numeric conversion VIs to convert the data to any representation that is needed on the host.
Message Edité par BenjaminR le 03-20-2008 07:58 AM
Benjamin R.
R&D Software Development Manager
http://www.fluigent.com/
Attachments:
FXP Properties.jpg ‏39 KB

Simultaneous I/O with DMA FIFO channels on cRio

Hy everybody,
I work on a CompactRio 9014, with NI 9263 for analog output and NI 9215 for analog input.
I want to do simultaneous acquisition and generation using DMA channels: one on the first channel for the input and the second on the second channel for the output.
I have already read the example CompactRio Simultaneous AI and AO streaming But, if in this example the Analog input is done by a DMA FIFO, the output is done using the FPGA host interface read/write node (register I/O).
In my case I try to use two DMA channels, one for transfering the input datas and the second to transmit the output datas from the RT vi to the fpga VI.
So I have configure two FIFOs, both of size of about 4000. My sampling rate (for input and output) at the level of the fpga is 20KHz. I want to output blocks of size 2000 and simultaneous read something that is directly linked to my output. The problem, (I suppose) is that I have to wait on the Invoke Node (wich read block from the Input FIFO) that the reading of the block is completed. In my application, things works well at the beginning but after some seconds the output become instable.
I think the way I program my simultaneous analog I/O is not correct, but I don't see the right way to do that with two DMA channels. I have attached my RT VI and my FPGA VI. (the probleme of I/O is in the case "faulse" in the Room_measurements VI)
I hope somebody can help me.
Thanks in advance for your answers
Attachments:
Room_measurement_RT.vi ‏339 KB
Room_measurement_FPGA.vi ‏566 KB

Hello,
I now try to separate in two timed loops the input and the output. Each of the loops run at 100ms. The first loop (generation loop) must generate a sinus during 15 seconds(So the loop must run 150 times because dt is 100ms). The second loop (input), must record an input during 30 seconds. I am also not sure if the timeouts parameters of the FIFO read/write are correct.
I think this way (see the jpg) is better. But I still have several problems:
When I launch my VI, it works at the beginning but stops after some seconds (in fact I loose the connexion)
Also, if I stop the output loop before that the input stops, the VI also stops.
I hope somebody can help me
I attache my last_VIs
Attachments:
testAOAI1.vi ‏388 KB
Room_measurement_FPGA1.vi ‏566 KB

DMA FIFO

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